Conclusion
MEC1404-NU integrates a MIPS32-based embedded controller, flexible host interfaces (LPC, eSPI, I2C/SMBus), extensive mixed-signal and digital peripherals, and a detailed power/clock/reset infrastructure into a single device optimized for notebook and tablet platforms. Its architecture supports:
- Firmware-based customization via secure boot from shared or private SPI/eSPI flash
- ACPI-compliant power management with multiple sleep depths, wake-capable events, and connected standby support
- Dense integration of keyboard, fan, thermal, debug, and miscellaneous IO functions into a single controller
- Robust host access models through LPC/eSPI, including SERIRQ, Port 80, EMI, and logical device BAR mapping
By relying on the described configuration and register structures, MEC1404-NU can be tailored to a wide range of platform designs, from legacy LPC-based systems to modern eSPI or SMBus-based architectures, while providing deterministic behavior in low-power and high-reliability scenarios.
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Frequently Asked Questions (FAQ)
- Q1. What host interfaces can MEC1404-NU use, and how are they selected?
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- A1. MEC1404-NU supports LPC, eSPI, or I2C/SMBus host interfaces (device-dependent). After reset, all host-interface pins default to GPIO inputs. Boot ROM loads firmware from shared or private SPI or eSPI flash. The loaded firmware then configures GPIO Pin Control registers to assign alternate functions for the chosen interface:
- - For LPC: assign GPIO034/040–043/044/061/063/064/067 as PCI CLK, LAD[3:0], LFRAME#, LPCPD#, SERIRQ, LRESET#, CLKRUN#; program LPC BAR and set LPC Activate=1.
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- - For eSPI: assign the same GPIOs as eSPI CLK, IO0–IO3, CS#, ALERT#, RESET#; program eSPI BAR and Activate.
- - For I2C host: configure selected SMBus ports’ GPIOs as SDA/SCL and enable the relevant SMBus controller in host mode.
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- Interface choice depends on the motherboard design and is fixed in firmware; unused host interfaces remain as GPIO.
- Q2. How does MEC1404-NU boot from different SPI flash sources or eSPI flash?
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- A2. MEC1404-NU uses Boot ROM with strapping options:
- - CR_STRAP on GPIO102/KSO09[CR_STRAP]:
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- - Low: Boot from private SPI interface (PVT_xxx).
- - High: Boot from shared SPI or eSPI flash channel.
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- - BSS_STRAP on GPIO123/SHD_CS#:
- - Selects between shared SPI and eSPI flash channel.
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- When eSPI flash is used, GPIO123 must also serve as RSMRST#. Boot ROM drives it high to activate the eSPI flash channel. After loading firmware into code SRAM, Boot ROM jumps to user code.
- Q3. How does MEC1404-NU manage different IO voltage levels on LPC/eSPI pins?
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- A3. The VTR_33_18 power pin supplies specific host-interface pins (GPIO034, 040–044, 061, 063, 064, 067). If LPC is used, VTR_33_18 must be tied to 3.3 V. If eSPI is used, it must be tied to 1.8 V. GPIOs on these pins can still operate as either 1.8 V or 3.3 V signals depending on that supply. For I2C host configurations, ten GPIOs powered by VTR_33_18 can be run at either voltage to match the host.
- Q4. Can MEC1404-NU operate in connected standby and how are low-power states configured?
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- A4. Yes. MEC1404-NU supports connected standby through its power-plane architecture (VBAT, VTR, VTR_33_18), 32 kHz and 48 MHz clock framework, and JTVIC wake events. Firmware configures:
- - Block-level sleep via EC_SLP_EN and HOST_SLP_EN registers
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- - System sleep type via SYS_SLP_CNTRL bits [2:0] (Heavy Sleep 1, 2, 3, Deepest Sleep)
- - Wake-capable interrupts via GIRQ Enable registers and wake event classification
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- The EC uses the WAIT instruction to enter sleep once all required blocks have deasserted clk_req. Wake events from timers, host interfaces, GPIO, and other blocks restart the 48 MHz oscillator and resume program execution according to configured sleep state.
- Q5. What is the role of GIRQ16 and GIRQ22 in MEC1404-NU’s wake behavior?
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- A5. GIRQ16 and GIRQ22 are dedicated wake-only interrupt groups:
- - GIRQ16: Generates both a wake event and a normal EC interrupt. It is used when firmware must act after a wake event (e.g., to parse incoming data or reconfigure blocks). EC firmware clears the source and may re-enter sleep.
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- - GIRQ22: Generates only a wake event with no EC interrupt. Hardware automatically starts the oscillator so peripheral logic can process the event, then clears the wake condition and returns to sleep without firmware intervention.
- Firmware typically enables these GIRQs just before executing the sleep instruction.
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- Q6. How does MEC1404-NU ensure LPC and eSPI accesses are routed to the right internal blocks?
- A6. MEC1404-NU uses Base Address Registers (BARs):
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- - IO_BARs: One per logical device, defining base LPC I/O addresses. Mask bits allow mapping of contiguous blocks (e.g., 0x60 & 0x64 for 8042).
- - Device Memory BARs: Map LPC memory cycles to AHB addresses of specific logical devices.
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- - SRAM Memory BARs: Map a host 4 kB window into internal code/data space.
- On each LPC cycle, the controller compares the address against all valid BARs; matching BARs “claim” the cycle and forward it to the target. Overlapping BARs set BAR_CONFLICT status in Host Bus Error register and can trigger an EC interrupt.
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- Q7. How is keyboard scanning implemented in MEC1404-NU, and can internal pull-ups be used?
- A7. The keyboard matrix scan interface supports up to 18×8 KSO/KSI matrix, multiplexed onto GPIO pins. For each key-scan pin:
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- - Pin Control registers select KSO/KSI alternate function and internal pull-ups if desired.
- - When internal pull-ups are used on KSI/KSO lines, PreDrive Mode must be enabled. PreDrive ensures outputs are driven to appropriate levels before scanning transitions, improving signal integrity and reducing ghost keys.
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- - EC firmware configures scanning rate, debouncing, and host reporting via 8042 and ACPI-EC interfaces.
- Q8. How does the Watchdog Timer (WDT) in MEC1404-NU work and what is its time base?
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- A8. The WDT is a 16-bit down-counter referenced to a 5 Hz derived clock:
- - WDT Load register sets the initial count value.
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- - Each decrement step takes 33/5 Hz clock cycles; at 32.768 kHz time base, this is ~1.007 ms per count.
- - The WDT is enabled by setting the Enable bit in the WDT Control register.
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- - Firmware must periodically reload the WDT (via Load register, Kick register, or WDT event) before underflow.
- - On underflow, WDT sets a status flag and generates a WDT event, which can lead to system reset or error handling depending on configuration.
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- Q9. Can the host access internal EC memory without EC firmware involvement in MEC1404-NU?
- A9. Yes, MEC1404-NU’s Embedded Memory Interface (EMI) allows the host to read and write two EC memory regions autonomously when:
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- - Regions are configured by EC firmware with base, read limit, and write limit.
- - Access type (8/16/32-bit, auto-increment) is chosen via EC Address LSB register.
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- - Host uses EMI address and data registers in LPC I/O space to generate linear memory accesses.
- The EC may mark regions as read-only, write-only, or read/write from the host perspective. EMI’s auto-increment mode supports efficient block transfers.
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- Q10. How does MEC1404-NU handle UART baud accuracy if no external 32 kHz clock is present?
- A10. Without an external 32.768 kHz reference, the 48 MHz ring oscillator can have up to ±4 % frequency variation. This can skew UART baud rates relative to a peer device with a more accurate clock, causing framing errors at higher speeds or tighter tolerance requirements. For robust UART communication, either an external 32 kHz clock or on-board frequency margin should be considered. The Clock Enable register selects whether the 48 MHz oscillator locks to external or internal 32 kHz.
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- Q11. What is the purpose of the VBAT-Powered Control Interface (VCI) and BGPO in MEC1404-NU?
- A11. VCI and BGPO provide battery-backed control signals:
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- - VBAT-Powered Control Interface (VCI):
- - Two active-low VCI inputs, one active-high VCI input, one active-high VCI output.
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- - Optional filtering and latching; used to detect and control external power events while main power is off.
- - Battery-Powered General Purpose Output (BGPO):
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- - Output driven from VBAT domain, allowing simple external logic control during system-off states (e.g., gating external LDOs or system indicators).
- These elements support fine-grained system power sequencing and state indication even when VCC or VTR_33_18 are off.
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- Q12. Does MEC1404-NU support secure firmware updates?
- A12. Yes. The secure Boot ROM loader supports:
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- - Up to four code images in shared flash.
- - Crisis recovery via keyboard matrix scan pins and dedicated crisis-recovery SPI interface.
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- - CRC-32 validation and AES-128 encryption of firmware images.
- These features allow robust firmware update mechanisms with integrity and confidentiality, while providing a fallback path in case of flash corruption.
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- Q13. How does MEC1404-NU handle test and debug access without disturbing sleep state?
- A13. MEC1404-NU’s ICSP-based EJTAG interface allows debug access. To minimize sleep disruption:
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- - SLEEPING status bit in MTAP registers can be read without re-enabling the 48 MHz oscillator.
- - Auto Clear Sleep and Sleep Debug bits in SYS_SLP_CNTRL are typically set before entering sleep so that after an ICSP wake, the EC can re-enter sleep automatically once debug tasks are done.
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- - Debug Done interrupt can be enabled as an alternative mechanism; firmware reconfigures sleep control when debug activity completes.