Wafer and CoWoS Driven, Huang Renxun: TSMC Capacity to Double in Next Decade

Recently, NVIDIA CEO Jensen Huang stated that the company is currently fully committed to Grace Blackwell production while also mass-producing Vera Rubin. Vera Rubin consists of six distinct chips, each representing the world's most advanced technology.

Considering the supply demands for these cutting-edge AI chips, Huang emphasized that TSMC must work exceptionally hard this year, as NVIDIA requires substantial wafer and CoWoS capacity.

Huang further noted that TSMC's capacity is likely to exceed 100% over the next decade. Production will be distributed across facilities in the United States, Europe, Japan, and Taiwan.

Driven by artificial intelligence and high-performance computing (HPC) chips, advanced process nodes and advanced packaging technologies are in short supply.

TSMC's latest advanced process—2nm (N2)—has commenced mass production in Q4 2025. Utilizing the first-generation Gate-All-Around (GAA) transistor architecture, it delivers a 10%-15% performance boost at equivalent power consumption compared to the previous-generation 3nm/3nm Enhanced (N3E). Conversely, it achieves a 25%-30% reduction in power consumption at equivalent performance while increasing transistor density by approximately 20%.

TSMC's Fab 20 in Baoshan and Fab 22 in Kaohsiung, Taiwan, serve as the initial production sites for the 2nm process. Capacity at both facilities for 2026 has been fully booked. TSMC also plans to construct a new 2nm fab in Hsinchu Science Park and adopt 2nm and A16 process technologies at its third fab in Arizona, USA, with mass production expected to commence in 2028.

Additionally, TSMC intends to commence mass production of its enhanced 2nm performance variant (N2P) in the second half of 2026. The company will also advance R&D for its next-generation 1.4nm process, targeting risk production trials in 2027 and phased mass production starting in 2028.

In advanced packaging, CoWoS technology represents TSMC's core competitive advantage. Global AI chip manufacturers heavily rely on CoWoS capacity, with the technology currently widely deployed in AI training and inference chips from companies like NVIDIA, AMD, Google, and Amazon to support large-scale model training and high-performance computing demands.

Given the ongoing CoWoS capacity shortage, the industry anticipates TSMC will gradually repurpose existing 8-inch fabs in Taiwan into advanced packaging facilities. Concurrently, currently under-construction advanced packaging plants will prioritize expanding CoWoS capacity as their primary objective. Beyond the already operational AP5B in Central Taiwan Science Park and AP6 in Zhunan, facilities including AP8 in Southern Taiwan Science Park and AP7 in Chiayi are preparing to expand CoWoS capacity to further meet market demand.