Preparing for the Future of High-Speed AI Interconnects, Marvell Announces PCIe 8.0 SerDes Demonstration

Marvell has announced it will showcase a suite of high-speed interconnect technologies for future AI demands at DesignCon 2026, held February 24-26 in California, USA. This includes PCIe 8.0 SerDes (Serializer/Deserializer) supporting a raw bit rate of 256 GT/s.

The PCIe 8.0 specification is currently in draft form, with finalization expected in 2028. In a ×16 lane configuration, PCIe 8.0 will deliver 1TB of bi-directional bandwidth, supporting high-load applications including AI/ML, high-speed networking, and other data-intensive workloads.

Marvell's PCIe 8.0 SerDes demonstration utilized TE Connectivity's AdrenaLINE Catapult connectors. At this exhibition, Marvell also showcased a 40GB HBM D2D interface, a 224G LR SerDes based on Copper in Common Package (CPC) interconnect, 200G/lane ACC cables, PCIe 6.0 AEC cables, and 1.6T AEC cables.