SK Hynix Develops AIP Process to Tackle Manufacturing Bottlenecks in 300+ Layer NAND

According to South Korean media outlet zdnet.co.kr, SK Hynix, a major South Korean memory chip manufacturer, is developing a next-generation process technology called AIP (All-In-Plug). The goal is to achieve high-stacked NAND Flash with over 300 layers while significantly reducing manufacturing costs.

Current NAND Flash production requires multiple critical etching steps. However, as stacking layers exceed 300, manufacturing costs and process complexity escalate dramatically. AIP technology focuses on the High Aspect Ratio Contact (HARC) etching process—a core step in NAND Flash manufacturing. By integrating multiple process stages and eliminating redundant steps, it aims to maintain process viability while lowering production costs and improving yield efficiency.

If AIP technology is successfully introduced into mass production, it is expected to significantly reduce the number of etching steps starting with next-generation NAND Flash like V11, establishing a more economical manufacturing foundation for memory chips with higher stacking layers.

SK Hynix Vice President Lee Sunghoon highlighted in his keynote address at SEMICON Korea 2026 that as semiconductor process complexity continues to escalate, relying on legacy technologies can no longer sustain future growth. Consequently, SK Hynix is establishing a predictable next-generation process technology platform while concurrently evaluating key technologies for the next generation of DRAM and NAND.

Lee Sunghoon stated that one key factor driving the cost increase of high-layer-count NAND Flash is the rise in etching process steps. Integrating multiple steps into a single process is now a critical technical challenge for the company.