LTC3774EUHE#PBF

Architecture and Core Operating Principles of the LTC3774

The LTC3774 employs a current-mode control architecture where the top MOSFET turns on at the beginning of each switching cycle when the internal oscillator sets an RS latch. The device turns off the top MOSFET when the main current comparator resets the latch, with the peak inductor current determined by the voltage on the ITH (current threshold) pin. This pin receives its signal from the error amplifier, which compares the remote sensed output voltage against an internal 0.6V reference.

The control loop operates through a feedback mechanism where the remote sense amplifier measures the differential voltage across the output capacitor and re-references it to the local IC ground. When load current increases, the output voltage decreases slightly, causing the error amplifier to increase the ITH voltage until the inductor's average current matches the new load requirement. After the top MOSFET turns off, the bottom MOSFET conducts until either the inductor current begins to reverse or the next cycle begins.

The LTC3774 incorporates an internal soft-start function that ramps the output voltage smoothly from zero to its final regulated value over approximately 600 microseconds. This prevents inrush currents and output overshoot during power-up. The controller can also be configured to track the output voltage of another supply, enabling coordinated multi-output power systems.

Sub-Milliohm DCR Current Sensing Technology in the LTC3774

The LTC3774's most significant innovation is its ability to sense inductor current through the inductor's own DCR with exceptional signal-to-noise ratio. Traditional current sensing methods employ discrete sense resistors, which dissipate power and reduce overall efficiency. The LTC3774 eliminates this loss by using the inductor's copper winding resistance as the sensing element.

The controller features two positive sense inputs: SNSD+ (DC current sense) and SNSA+ (AC current sense). The SNSD+ pin connects to a filter with a time constant matched to the inductor's L/DCR ratio, while the SNSA+ pin connects to a filter with one-fifth that time constant. This dual-filter architecture provides a 14dB improvement in signal-to-noise ratio compared to conventional single-filter approaches, enabling reliable operation with DCR values as low as 0.2 milliohms.

The maximum current sense voltage is programmable from 10mV to 30mV in 5mV increments using the ILIM pin, allowing precise current limit adjustment. The relationship between DCR, inductor value, and sense voltage is expressed as:

DCR = V_SENSE(MAX) / (I_MAX + ΔI_L/2)

where V_SENSE(MAX) is the maximum sense voltage, I_MAX is the maximum load current, and ΔI_L is the inductor ripple current.

Proper PCB layout is critical for DCR sensing performance. The sense lines must run close together to a Kelvin connection directly beneath the current sense element, with filter capacitors placed immediately adjacent to the IC pins. Parasitic resistance, capacitance, and inductance in the sense circuit can degrade signal integrity and make the programmed current limit unpredictable.

Dual-Channel and Multi-Phase Capabilities of the LTC3774

The LTC3774 integrates two independent control channels on a single die, each capable of driving separate power stages. This dual-channel architecture enables designers to implement 2-phase converters with a single IC, or to combine multiple LTC3774 devices for higher phase counts.

The controller supports multiphase operation through daisy-chaining, where the CLKOUT output of one device connects to the MODE/PLLIN input of the next. Up to six LTC3774 controllers can be paralleled to create 1-, 2-, 3-, 4-, 6-, 8-, or 12-phase systems. The PHSMD pin controls the phase relationship between channels, allowing phase differences of 60°, 90°, 120°, 180°, 240°, or 45° depending on the pin configuration.

Multiphase operation distributes the load current across multiple power stages, reducing individual MOSFET stress and improving thermal distribution. The interleaved switching reduces input and output voltage ripple, allowing the use of smaller filter capacitors. For example, a 12-phase system operating at 400kHz effectively produces a 4.8MHz ripple frequency at the output, significantly reducing filtering requirements compared to a single-phase implementation.

Voltage Regulation and Remote Sensing Features of the LTC3774

The LTC3774 includes a precision 0.6V internal reference and dual differential remote output voltage sense amplifiers. These amplifiers feature high input impedance and low offset voltage, enabling accurate voltage regulation even in high-current, low-voltage applications where PCB trace losses are significant.

The output voltage is set by an external resistive divider connected across the load, with the relationship:

V_OUT = 0.6V × (1 + R_D1/R_D2)

The remote sense amplifier measures the voltage at the load rather than at the controller, compensating for voltage drops in PCB traces and connectors. The V_OSNS+ and V_OSNS- sense lines must be routed as a tightly coupled pair directly to the load, ideally shielded by a ground plane to maintain signal integrity.

The controller achieves ±0.75% maximum total DC output error over temperature, accounting for reference voltage tolerance, amplifier offset, and feedback divider accuracy. This precision enables reliable operation of sensitive digital loads that require tight voltage regulation.

Operating Modes and Light Load Efficiency in the LTC3774

The LTC3774 supports three distinct operating modes selectable via the MODE/PLLIN pin: Burst Mode operation, pulse-skipping mode, and forced continuous mode. Each mode represents a different approach to managing efficiency at light loads.

In Burst Mode operation, the controller enters a sleep state when the load current drops below a threshold. During sleep, both MOSFETs turn off and the output capacitor supplies the load. As the output voltage decreases, the error amplifier output rises, eventually triggering the controller to resume normal operation. This mode minimizes switching losses at light loads, achieving the highest efficiency but producing higher output ripple and potential audio noise.

Pulse-skipping mode operates at constant frequency but skips switching cycles when the load current is light. The current comparator remains tripped for multiple cycles, forcing the top MOSFET to stay off. This mode provides lower output ripple than Burst Mode while maintaining reasonable light-load efficiency.

Forced continuous mode keeps the MOSFETs switching at every cycle regardless of load. The inductor current is allowed to reverse at light loads, producing the lowest output ripple and minimal audio noise, but at the cost of reduced light-load efficiency compared to Burst Mode.

The transition between modes occurs at the TK/SS pin voltage of 0.5V to 0.565V, where the controller operates in forced continuous mode to minimize output ripple during soft-start, ensuring a clean power-good signal.

Frequency Control and Phase-Locked Loop Synchronization in the LTC3774

The LTC3774 provides flexible frequency control through the FREQ pin, which accepts a precision 20-microampere current source. A single resistor to ground sets the switching frequency across the 200kHz to 1.2MHz range. This allows designers to optimize the frequency-efficiency tradeoff: lower frequencies reduce MOSFET switching losses but require larger inductors and capacitors, while higher frequencies enable smaller components but increase switching losses.

The integrated phase-locked loop (PLL) enables synchronization to an external clock signal applied to the MODE/PLLIN pin. The PLL comprises a voltage-controlled oscillator (VCO) and an edge-sensitive phase detector that provides zero-degree phase shift between the external and internal oscillators. The phase detector output drives complementary current sources that charge or discharge an integrated filter network, adjusting the VCO frequency until it matches the external clock.

When an external clock is detected, the internal switch isolates the FREQ pin from the PLL filter network, preventing frequency drift. The controller operates in forced continuous mode when synchronized to an external clock. The PLL can lock to any frequency within the 200kHz to 1.2MHz range, provided the frequency setting resistor is present to establish the initial VCO frequency.

Protection and Fault Management Features of the LTC3774

The LTC3774 incorporates multiple protection mechanisms to safeguard against fault conditions. The power-good (PGOOD) output is an open-drain signal that pulls low when the output voltage deviates more than ±7.5% from the 0.6V reference, when the RUN pin is below 1.14V, or during soft-start and tracking phases. An internal 45-microsecond power-bad mask prevents false triggering during transient events.

An overvoltage comparator monitors the output voltage and turns off the top MOSFET while turning on the bottom MOSFET if the output exceeds 7.5% above the regulated value. This protects downstream circuitry from transient overshoot.

The controller implements current foldback to limit short-circuit current. When the output voltage falls below 50% of its nominal value, the maximum sense voltage progressively decreases from its programmed value to one-third of that value. Under severe short-circuit conditions with very low duty cycles, the controller enters cycle-skipping mode to further limit current. The short-circuit current is determined by:

I_SC = (V_SENSE(MAX)/3 / R_SENSE) - (ΔI_L(SC)/2)

where ΔI_L(SC) is the short-circuit ripple current determined by the minimum on-time and inductor value.

Upon removal of a short circuit, the output soft-starts using the internal soft-start ramp, reducing overshoot that would otherwise occur if the output capacitors had been charged at current limit.

Thermal Management and Temperature Compensation in the LTC3774

The LTC3774 features an integrated NTC (negative temperature coefficient) thermistor interface for DCR temperature compensation. The inductor's DCR increases approximately 0.4% per degree Celsius, reducing the current limit as temperature rises. The ITEMP pin accepts a constant 30-microampere current source and connects to an NTC thermistor network placed near the inductor.

The temperature compensation equation is:

V_SENSEMAX(ADJ) = V_SENSE(MAX) × (2 - V_ITEMP/2.8) / 1.5

where V_SENSEMAX(ADJ) is the adjusted maximum sense voltage and V_ITEMP is the voltage on the ITEMP pin.

The valid compensation range extends from 1.4V (no correction) to 0.6V (maximum correction). For duty cycles below 25%, the range extends to 0V. Designers can linearize the nonlinear NTC thermistor response by adding series and parallel resistors to the network.

The ITEMP pin can also be used to adjust V_SENSE(MAX) to values between the nominal 10mV, 15mV, 20mV, 25mV, and 30mV settings for more precise current limit tuning. This capability applies to both DCR sensing and discrete sense resistor applications.

Component Selection and Design Considerations for LTC3774 Applications

Inductor selection begins with determining the required inductance value based on the desired ripple current. A reasonable starting point is to limit ripple current to approximately 40% of the maximum output current. The inductance is calculated as:

L ≥ (V_IN - V_OUT) / (f_OSC × I_RIPPLE) × (V_OUT / V_IN)

where f_OSC is the switching frequency and I_RIPPLE is the maximum acceptable ripple current.

Ferrite core inductors are preferred for the LTC3774 due to their low core loss at high switching frequencies. Ferrite cores saturate abruptly when peak current is exceeded, causing inductance to collapse and output ripple to increase dramatically. Designers must ensure the inductor's saturation current rating exceeds the peak inductor current, which equals the maximum DC current plus half the ripple current.

The DCR of the selected inductor must satisfy the maximum sense voltage requirement:

DCR = V_SENSE(MAX) / (I_MAX + ΔI_L/2)

For high-current applications, inductors with DCR values below 1 milliohm are preferred to minimize conduction losses.

Power MOSFET selection requires careful consideration of on-resistance, input capacitance, and voltage rating. The top MOSFET experiences both conduction losses and transition losses, with transition losses becoming significant at input voltages above 15V. The transition loss term depends on the Miller capacitance (C_MILLER), which is derived from the MOSFET's gate charge curve:

C_MILLER = (Q_gate_b - Q_gate_a) / V_DS

where Q_gate_a and Q_gate_b are gate charges at the beginning and end of the Miller plateau.

The bottom synchronous MOSFET primarily experiences conduction losses, with power dissipation given by:

P_SYNC = [(V_IN - V_OUT) / V_IN] × (I_MAX)² × (1 + δ) × R_DS(ON)

where δ is the temperature coefficient of on-resistance, typically 0.005/°C for low-voltage MOSFETs.

Input capacitor selection is driven by the maximum RMS current requirement:

C_IN Required I_RMS ≈ I_MAX / V_IN × [(V_OUT) × (V_IN - V_OUT)]^(1/2)

This formula peaks at V_IN = 2×V_OUT, where I_RMS = I_OUT/2. Multiple capacitors may be paralleled to meet size or height constraints. Ceramic capacitors with X7R or X5R dielectric are preferred for their low ESR and high frequency response, though care must be taken to account for voltage and temperature derating.

Output capacitor selection is driven by the effective series resistance (ESR) requirement to limit output ripple:

ΔV_OUT ≈ ΔI_RIPPLE × (ESR + 1/(8×f×C_OUT))

The output ripple is highest at maximum input voltage. For applications requiring less than 50mV ripple at maximum V_IN with 40% inductor ripple current, the ESR requirement is:

C_OUT Required ESR < N × R_SENSE

where N is the number of phases.

PCB Layout and Signal Integrity for LTC3774 Implementations

Proper PCB layout is critical for achieving the performance specified in the LTC3774 datasheet. The INTVCC decoupling capacitor must be placed immediately adjacent to the IC between the INTVCC pin and ground plane. A 1-microfarad ceramic capacitor of X7R or X5R type should be supplemented with 4.7 to 10 microfarads of additional low-ESR capacitance.

The feedback divider should be placed directly across the output capacitor terminals, with V_OSNS+ and V_OSNS- routed as a tightly coupled pair from the IC to the feedback divider with minimum trace spacing. These sensitive traces must be kept away from high-speed switching nodes, ideally shielded by a ground plane.

The current sense filter capacitors (C1 and C2) must be placed as close as possible to the SNSA+, SNSD+, and SNS- pins. The sense lines should run together with minimum spacing to a Kelvin connection directly beneath the inductor's current sense element. Parasitic inductance in these traces can couple switching noise into the sense signal, degrading current limit accuracy.

The input capacitor positive plate should connect to the drain of the top MOSFET as closely as possible to minimize the loop inductance of the high-current switching path. The output capacitor ground should return to the negative terminal of the input capacitor through a short, isolated trace, not sharing a common ground path with switched current paths.

A modified "star ground" technique should be employed, with a low-impedance, large copper area central grounding point on the same side of the PCB as the input and output capacitors. This point should provide tie-ins for the INTVCC decoupling capacitor, the feedback divider, and the IC ground pin.

The PWM and switch nodes should be routed away from sensitive small-signal nodes, with high dv/dt traces separated by ground traces or ground planes. The ITH compensation capacitor (47pF to 330pF) should be placed as close as possible to the IC.

Conclusion

The LTC3774 dual-channel synchronous step-down controller represents a sophisticated solution for high-efficiency power conversion across a wide range of input and output voltages. Its proprietary sub-milliohm DCR current sensing technology eliminates the efficiency losses associated with discrete sense resistors, enabling power densities and efficiencies previously unattainable in multiphase buck converter designs. The controller's support for up to 12-phase operation, integrated phase-locked loop, and comprehensive protection features make it suitable for demanding applications in computing systems, telecommunications infrastructure, and industrial equipment. Successful implementation requires careful attention to component selection, particularly regarding inductor DCR and MOSFET characteristics, as well as meticulous PCB layout to maintain signal integrity in the current sense and feedback paths. The flexibility to operate in multiple modes—Burst Mode, pulse-skipping, and forced continuous—allows designers to optimize efficiency across the full load range, from light standby conditions to maximum output current.

Frequently Asked Questions (FAQ)

Q1. What is the significance of the LTC3774's sub-milliohm DCR current sensing capability compared to traditional sense resistor approaches?

A1. The LTC3774 uses the inductor's own DC winding resistance as the current sense element, eliminating the conduction losses associated with discrete sense resistors. This approach improves efficiency by reducing I²R losses in the power path. The dual-filter architecture (SNSD+ and SNSA+) provides a 14dB signal-to-noise ratio improvement, enabling reliable operation with DCR values as low as 0.2 milliohms. In high-current applications, this can translate to efficiency improvements of 2-5% compared to sense resistor-based designs, with the benefit increasing as output current increases.

Q2. How does the LTC3774 support multiphase operation, and what are the advantages of using multiple phases?

A2. The LTC3774 can be daisy-chained with up to six devices to create 1-, 2-, 3-, 4-, 6-, 8-, or 12-phase systems. The CLKOUT output of one device connects to the MODE/PLLIN input of the next, with the PHSMD pin controlling phase relationships. Multiphase operation distributes load current across multiple power stages, reducing individual MOSFET stress and improving thermal distribution. The interleaved switching reduces input and output voltage ripple by a factor equal to the number of phases, allowing the use of smaller, lower-cost filter capacitors. For example, a 12-phase system at 400kHz produces an effective 4.8MHz ripple frequency, significantly reducing filtering requirements.

Q3. What is the role of the TK/SS pin in the LTC3774, and how does it enable output voltage tracking?

A3. The TK/SS (tracking/soft-start) pin controls the output voltage ramp rate during startup and enables tracking of another supply's output. During normal soft-start operation, an internal 1.25-microampere current source charges an external capacitor connected to this pin, creating a linear voltage ramp from 0V to 0.6V over approximately 600 microseconds. The output voltage rises proportionally to this ramp. For output tracking applications, an external resistive divider from another supply connects to the TK/SS pin, causing the LTC3774's output to track that supply's voltage ramp. This enables coordinated startup of multiple power rails, preventing one supply from rising faster than another and potentially damaging downstream circuitry.

Q4. How does the LTC3774's current foldback protection function during short-circuit conditions?

A4. When the output voltage falls below 50% of its nominal value, the LTC3774 progressively reduces the maximum sense voltage from its programmed value to one-third of that value. This limits the short-circuit current to approximately one-third of the normal maximum current. Under severe short-circuit conditions with very low duty cycles, the controller enters cycle-skipping mode, turning off the top MOSFET for multiple cycles to further limit current. Upon short-circuit removal, the output soft-starts using the internal ramp, reducing overshoot that would otherwise occur if the output capacitors had been charged at full current limit. This soft recovery minimizes stress on the power stage and downstream components.

Q5. What are the key differences between Burst Mode, pulse-skipping, and forced continuous mode operation in the LTC3774?

A5. Burst Mode operation achieves the highest light-load efficiency by entering sleep mode when load current drops below a threshold, with both MOSFETs off and the output capacitor supplying the load. However, this produces higher output ripple and potential audio noise. Pulse-skipping mode operates at constant frequency but skips switching cycles at light loads, providing lower ripple than Burst Mode while maintaining reasonable efficiency. Forced continuous mode keeps the MOSFETs switching every cycle regardless of load, allowing inductor current to reverse at light loads. This produces the lowest output ripple and minimal audio noise but sacrifices light-load efficiency. The selection depends on the application's priorities: Burst Mode for maximum efficiency, pulse-skipping for a balance, and forced continuous for minimum ripple and noise.

Q6. How should the ITEMP pin be configured for DCR temperature compensation, and why is this necessary?

A6. The ITEMP pin connects to an NTC thermistor network placed near the inductor. The thermistor's resistance decreases as temperature increases, causing the ITEMP voltage to decrease. This triggers the LTC3774 to increase the maximum sense voltage according to the equation: V_SENSEMAX(ADJ) = V_SENSE(MAX) × (2 - V_ITEMP/2.8) / 1.5. This compensation is necessary because inductor DCR increases approximately 0.4% per degree Celsius. Without compensation, the current limit would decrease as the inductor heats up, potentially causing the converter to operate below its rated current at elevated temperatures. Proper compensation maintains consistent current limit performance across the full operating temperature range, typically 25°C to 100°C.

Q7. What PCB layout practices are most critical for maintaining current sense signal integrity in LTC3774 designs?

A7. The current sense filter capacitors (C1 and C2) must be placed immediately adjacent to the SNSA+, SNSD+, and SNS- pins. The sense lines should run together as a tightly coupled pair with minimum spacing to a Kelvin connection directly beneath the inductor's current sense element. Parasitic resistance, capacitance, and inductance in these traces can couple switching noise into the sense signal, degrading current limit accuracy and causing unpredictable behavior. The sense traces must be kept away from high-speed switching nodes, ideally shielded by a ground plane. Additionally, the feedback divider should be placed directly across the output capacitor terminals, with V_OSNS+ and V_OSNS- routed as a coupled pair from the IC to the feedback divider. These practices maintain signal integrity and ensure the programmed current limit remains accurate.

Q8. How does the LTC3774's phase-locked loop enable synchronization to external clock sources, and what are the benefits?

A8. The LTC3774 integrates a phase-locked loop comprising a voltage-controlled oscillator (VCO) and an edge-sensitive phase detector. When an external clock signal is applied to the MODE/PLLIN pin, the phase detector compares the rising edges of the external and internal oscillators, generating complementary current sources that charge or discharge an integrated filter network. This adjusts the VCO frequency until it matches the external clock with zero-degree phase shift. The controller operates in forced continuous mode when synchronized. Benefits include the ability to synchronize multiple converters to a system clock, reducing EMI by controlling switching frequency, and enabling coordinated operation in multiphase systems. The PLL can lock to any frequency within the 200kHz to 1.2MHz range.

Q9. What factors should be considered when selecting the switching frequency for an LTC3774 application?

A9. Switching frequency selection involves a tradeoff between efficiency and component size. Lower frequencies reduce MOSFET switching losses and transition losses, improving efficiency but requiring larger inductors and capacitors to maintain acceptable output ripple. Higher frequencies enable smaller components but increase switching losses and gate drive losses. The optimal frequency depends on the specific application requirements. For high-efficiency, low-ripple applications, frequencies of 200-400kHz are typical. For space-constrained designs, frequencies of 800kHz to 1.2MHz may be preferred despite lower efficiency. The frequency setting resistor connected to the FREQ pin determines the operating frequency, with a precision 20-microampere current source providing the bias current. The relationship between FREQ pin voltage and switching frequency is provided in the datasheet's typical performance characteristics.

Q10. How should power MOSFETs be selected for the LTC3774, and what are the key performance parameters?

A10. The top MOSFET should have low input capacitance (low gate charge) to minimize transition losses, particularly at high input voltages above 15V. The Miller capacitance (C_MILLER) is the most important selection criterion for the top switch. The bottom synchronous MOSFET should have low on-resistance (R_DS(ON)) to minimize conduction losses. Both MOSFETs must be logic-level threshold devices compatible with the 5.5V INTVCC supply. The on-resistance temperature coefficient (typically 0.005/°C) must be considered when calculating power dissipation at elevated junction temperatures. For applications with V_IN much greater than V_OUT, a higher R_DS(ON) device with lower C_MILLER may actually provide higher efficiency than a lower R_DS(ON) device due to reduced transition losses. The absolute maximum voltage rating (BV_DSS) must exceed the maximum input voltage, with many logic-level MOSFETs limited to 30V or less.

Q11. What is the purpose of the PGOOD output, and how should it be used in system designs?

A11. The PGOOD (power good) output is an open-drain signal that indicates whether the output voltage is within regulation. PGOOD pulls low when the output voltage deviates more than ±7.5% from the 0.6V reference, when the RUN pin is below 1.14V, or during soft-start and tracking phases. An internal 45-microsecond power-bad mask prevents false triggering during transient events. In system designs, PGOOD typically connects to a system microcontroller or sequencing circuit to indicate when the power supply is ready to enable downstream circuitry. An external pull-up resistor (typically 10kΩ) to a 3.3V or 5V supply is required. PGOOD can also be used to trigger fault recovery sequences or to inhibit other power supplies if this converter fails to regulate properly.

Q12. How does the LTC3774 handle startup into a pre-biased output, and why is this capability important?

A12. The LTC3774 prevents discharge of pre-biased outputs by disabling both the top and bottom MOSFETs until the TK/SS pin voltage and internal soft-start voltage exceed the V_OSNS+ pin voltage. When V_OSNS+ is higher than TK/SS or the internal soft-start voltage, the error amplifier output is railed low, which would normally turn on the bottom MOSFET to discharge the output. However, both MOSFETs remain disabled, preventing discharge. When TK/SS and the internal soft-start both cross 500mV or V_OSNS+, whichever is lower, both MOSFETs are enabled. If the pre-bias exceeds the overvoltage threshold, the bottom gate turns on immediately to pull the output back into regulation. This capability is important in systems where multiple power supplies must start sequentially or where residual charge must be preserved on output capacitors during power cycling.