LTC1068IG#PBF

Architectural Foundation of the LTC1068 Series: Four Integrated 2nd Order Filter Sections

The LTC1068 series architecture consists of four identical, independently configurable 2nd order filter sections. Each section functions as a complete filter building block with its own set of input and output pins. This modular approach allows designers to implement various filter topologies by selecting appropriate operating modes and interconnection schemes.

Each 2nd order section contains internal operational amplifiers and switched-capacitor networks that perform the filtering function. The sections are matched to one another, meaning their performance characteristics track across temperature and supply voltage variations. This matching is particularly valuable when designing higher-order filters, as it ensures consistent performance across cascaded stages.

The four sections can be configured independently or cascaded together. For example, two sections can be combined to create a 4th order filter, or all four sections can be cascaded to create an 8th order filter. Alternatively, all four sections can operate independently as separate 2nd order filters for applications requiring multiple filtering channels.

Clock-to-Center Frequency Ratio Variants in the LTC1068 Series: Selecting the Right Model for Your Application

The LTC1068 series is offered in four distinct variants, each with a different internal clock-to-center frequency ratio. This ratio determines the relationship between the external clock frequency applied to the device and the resulting center frequency (or cutoff frequency) of the filter.

The LTC1068-200 variant features a 200:1 clock-to-center frequency ratio, making it suitable for ultralow frequency applications. This variant can implement lowpass or highpass filters with center frequencies ranging from 0.5 Hz to 25 kHz, and bandpass or bandreject filters from 0.5 Hz to 15 kHz.

The standard LTC1068 variant provides a 100:1 clock-to-center frequency ratio, offering a balanced approach for general-purpose filtering applications. It supports lowpass or highpass filters from 1 Hz to 50 kHz, and bandpass or bandreject filters from 1 Hz to 30 kHz.

The LTC1068-50 variant implements a 50:1 clock-to-center frequency ratio and is optimized for low-power, single-supply operation. It enables lowpass or highpass filters from 2 Hz to 50 kHz, and bandpass or bandreject filters from 2 Hz to 30 kHz.

The LTC1068-25 variant provides a 25:1 clock-to-center frequency ratio, enabling the highest frequency operation among the family members. This variant supports lowpass or highpass filters from 4 Hz to 200 kHz, and bandpass or bandreject filters from 4 Hz to 140 kHz.

The selection among these variants depends on the target frequency range of the application. For applications requiring very low frequency filtering, the LTC1068-200 is appropriate. For standard audio and instrumentation applications, the LTC1068 or LTC1068-50 are suitable choices. For high-frequency signal processing, the LTC1068-25 provides the necessary bandwidth.

Frequency Range Capabilities and Operating Specifications of the LTC1068 Series

The frequency range capabilities of the LTC1068 series are determined by both the internal clock-to-center frequency ratio and the maximum clock frequency that can be reliably applied to the device. The maximum clock frequency is limited by the switching speed of the internal switched-capacitor networks and the stability of the filter response.

For the LTC1068-200, the maximum center frequency of 25 kHz is achieved with a clock frequency of 5 MHz. For the standard LTC1068, a maximum center frequency of 50 kHz corresponds to a 5 MHz clock. The LTC1068-50 can achieve a maximum center frequency of 50 kHz with a 2.5 MHz clock, while the LTC1068-25 reaches a maximum center frequency of 200 kHz with an 8 MHz clock.

The minimum frequency operation is limited by the minimum practical clock frequency, which is typically around 100 Hz for most applications. Below this frequency, clock jitter and other timing artifacts become problematic. The actual minimum frequency achievable depends on the specific variant and the clock source quality.

The center frequency accuracy of each 2nd order section is specified as ±0.3% typical and ±0.8% maximum. This accuracy is maintained across the operating temperature range and supply voltage variations, making the LTC1068 series suitable for applications where precise frequency tuning is required.

Electrical Performance Characteristics of the LTC1068 Series: Noise, Accuracy, and Power Consumption

The noise performance of the LTC1068 series is one of its distinguishing characteristics. Each variant is specified with different noise levels depending on its intended application and power consumption profile.

The LTC1068-200 variant produces 50 μV RMS of noise per 2nd order section when the quality factor (Q) is 5 or less. The standard LTC1068 also produces 50 μV RMS under the same conditions. The LTC1068-50 variant generates 75 μV RMS, while the LTC1068-25 produces 90 μV RMS. These noise specifications represent the total wideband noise of the device and include contributions from the internal operational amplifiers and switched-capacitor networks.

The noise performance is dependent on the Q value of the filter section. Higher Q values result in increased noise levels due to the higher gain in the passband. For applications requiring very low noise performance, the LTC1068 and LTC1068-200 variants are preferred.

Power consumption varies among the variants based on their design optimization. The LTC1068-50 is optimized for low-power operation and draws only 4.5 mA from a single 5V supply. This makes it particularly suitable for battery-powered or power-constrained applications. The other variants consume slightly more current but remain within reasonable limits for most applications.

The output DC offset of each 2nd order section is specified as less than 5 mV typical, ensuring that the filter output remains centered around the expected DC level. This low offset is maintained across the operating temperature range.

Power Supply Configuration Options for the LTC1068 Series: Dual Supply, Single 5V, and Single 3.3V Operation

The LTC1068 series offers flexible power supply options to accommodate various system architectures. The device can operate with dual supplies (±5V), a single 5V supply, or a single 3.3V supply, providing designers with options that match their existing power distribution infrastructure.

For dual supply operation, the device is powered with +5V and -5V supplies, with the analog ground pin (AGND) serving as the reference point. This configuration provides the widest dynamic range and is suitable for applications where both positive and negative signal excursions are required.

Single 5V supply operation is achieved through an internal resistive divider that biases the analog ground pin to approximately 0.5 times the supply voltage (2.5V for the LTC1068, LTC1068-200, and LTC1068-25, or 2.175V for the LTC1068-50). This creates a virtual ground point that allows the filter to process signals around this midpoint. Single supply operation reduces the number of power supply rails required and simplifies the power distribution design.

Single 3.3V supply operation is also supported, making the LTC1068 series compatible with modern low-voltage digital systems. The internal biasing automatically adjusts to accommodate the lower supply voltage while maintaining performance specifications.

The total supply voltage (from V+ to V-) must not exceed 12V, and the device is rated for operation with supply voltages as low as 3.3V. The absolute maximum ratings specify that the input voltage at any pin must remain within V- - 0.3V to V+ + 0.3V to prevent damage to the device.

Pin Functions and Signal Integrity Considerations in LTC1068 Series Implementation

The 28-pin SSOP package of the LTC1068 series contains power supply pins, analog ground pins, clock input pins, and signal input/output pins for each of the four 2nd order filter sections.

The V+ and V- power supply pins should each be bypassed with 0.1 μF capacitors connected to the analog ground plane. These bypass capacitors should be placed as close as possible to the device pins to minimize the inductance of the connection. The power supplies should be isolated from other digital or high-voltage analog supplies to prevent noise coupling into the filter.

The analog ground pin (AGND) is the reference point for all internal analog circuits. The quality of the analog signal ground directly affects the filter's performance. An analog ground plane surrounding the package is recommended, with the plane connected to any digital ground at a single point only. This single-point connection prevents ground loops that could introduce noise into the filter.

For single supply operation, the AGND pin should be bypassed to the analog ground plane with at least a 0.47 μF capacitor. This capacitor provides a low-impedance path for high-frequency noise and helps stabilize the internal biasing voltage.

The clock input pin accepts TTL or CMOS logic signals with a 50% duty cycle (±10%). The clock source should have a separate power supply that is not shared with the filter's power supply. The clock signal should be routed from the right side of the IC package and perpendicular to it to avoid coupling to any input or output analog signal. A 200 Ω resistor can be placed between the clock source and the clock input pin to slow down the clock rise and fall times, further reducing charge coupling.

Each 2nd order section has three output pins: a lowpass (LP) output, a bandpass (BP) output, and a highpass/notch (HP/N) output. These outputs typically source 17 mA and sink 6 mA. Driving coaxial cables or resistive loads less than 20 kΩ will degrade the total harmonic distortion performance of the filter. When evaluating distortion or noise performance, the final output should be buffered with a wideband, noninverting high slew rate amplifier.

The inverting input pins of the internal operational amplifiers are susceptible to stray capacitive coupling from low-impedance signal outputs and power supply lines. In the printed circuit layout, any signal trace, clock source trace, or power supply trace should be at least 0.1 inches away from any inverting input pins.

The summing input pins are voltage input pins that should be driven with a source impedance below 5 kΩ. When not used, they should be tied to the analog ground pin. The summing pin connections determine the circuit topology (mode) of each 2nd order section.

Operating Modes of the LTC1068 Series: Achieving Flexible Filter Topologies Through External Resistor Configuration

The LTC1068 series supports multiple operating modes that allow designers to achieve different clock-to-center frequency ratios and transfer functions. The choice of operating mode affects both the frequency response and the output characteristics of each 2nd order section.

Mode 1 is the simplest configuration, where the clock-to-center frequency ratio is internally fixed at the part's nominal ratio. In this mode, external resistors are not required for frequency tuning. Mode 1 provides notch, lowpass, and bandpass outputs and is suitable for high-order Butterworth lowpass filters, low Q notches, and cascading 2nd order bandpass functions tuned at the same center frequency. Mode 1 operates faster than other modes due to its simpler architecture.

Mode 1b is derived from Mode 1 and includes two additional resistors (R5 and R6) that lower the amount of voltage fed back from the lowpass output into the input of the switched-capacitor summer. This allows the filter's clock-to-center frequency ratio to be adjusted beyond the part's nominal ratio. Mode 1b maintains the speed advantages of Mode 1 and is considered optimal for high Q designs with clock-to-cutoff frequency ratios greater than the part's nominal ratio. The parallel combination of R5 and R6 should be kept below 5 kΩ.

Mode 3 is the classical state variable configuration, where the clock-to-center frequency ratio can be adjusted above or below the part's nominal ratio. Mode 3 provides highpass, bandpass, and lowpass 2nd order filter functions. Mode 3 is slower than Mode 1 but offers greater flexibility in frequency tuning. Mode 3 is suitable for high-order all-pole bandpass, lowpass, and highpass filters.

Mode 2 is a combination of Mode 1 and Mode 3, where the clock-to-center frequency ratio is always less than the part's nominal ratio. Mode 2 provides less sensitivity to resistor tolerances than Mode 3 and offers a highpass notch output where the notch frequency depends solely on the clock frequency.

The choice of operating mode involves considerations beyond just adjusting the clock-to-center frequency ratio. The transfer function at the HP/N pins differs depending on the mode used. Mode 1 yields a notch transfer function, Mode 3 yields a highpass transfer function, and Mode 2 yields a highpass notch transfer function. More complex transfer functions, such as lowpass notch, allpass, or complex zeros, are achieved by summing two or more of the LP, BP, or HP/N outputs.

Stability and Performance Optimization in LTC1068 Series Designs: Operating Limits and Compensation Techniques

The stability of an LTC1068 series filter design is determined by the maximum Q value that can be achieved at a given center frequency and power supply voltage. The Maximum Q vs Center Frequency graphs in the device documentation define an upper limit of operating Q for each 2nd order section. These graphs indicate the conditions under which a filter will remain stable when operated at temperatures of 70°C or less.

For a 2nd order section, a bandpass gain error of 3 dB or less is arbitrarily defined as a condition for stability. When the passband gain error begins to exceed 1 dB, the use of a compensation capacitor (CC) connected from the lowpass node to the inverting node of a 2nd order section will reduce the gain error. The value of CC can be best determined experimentally, and as a guide, it should be about 5 pF for each 1 dB of gain error and should not exceed 15 pF.

When operating an LTC1068 series device near the limits defined by the Maximum Q vs Frequency graphs, passband gain variations of 2 dB or more should be expected. This is a normal characteristic of high-Q filter designs and does not indicate a problem with the device.

The stability of the filter is also affected by the cascade sequence of the 2nd order sections. When multiple sections are cascaded, the order in which they are connected affects the overall noise performance and stability. Generally, sections with lower Q values should be placed before sections with higher Q values to minimize noise accumulation.

Clock Signal Requirements and Routing Guidelines for the LTC1068 Series

The clock signal applied to the LTC1068 series must meet specific requirements to ensure proper operation and minimize noise coupling into the filter. Any TTL or CMOS clock source with a square-wave output and 50% duty cycle (±10%) is an adequate clock source for the device.

The clock source should have a separate power supply that is not shared with the filter's power supply. This isolation prevents noise from the clock generation circuit from coupling into the filter through the power supply rails. The analog ground for the filter should be connected to the clock's ground at a single point only, preventing ground loops.

The clock signal threshold levels depend on whether the device is operating with dual or single supply. For dual supply operation (±5V), the clock low level must be between -5V and 0V, and the clock high level must be between 0V and +5V. For single 5V supply operation, the clock low level must be between 0V and 1.5V, and the clock high level must be between 4.6V and 5V.

A pulsed generator can be used as a clock source provided the high level ON time is at least 25% of the pulse period. Sine waves are not recommended for clock input frequencies less than 100 kHz, since excessively slow clock rise or fall times generate internal clock jitter. The maximum clock rise or fall time should not exceed 1 μs.

The clock signal should be routed from the right side of the IC package and perpendicular to it to avoid coupling to any input or output analog signal. A 200 Ω resistor between the clock source and the clock input pin will slow down the rise and fall times of the clock to further reduce charge coupling.

Output Characteristics and Load Driving Capabilities of the LTC1068 Series

Each 2nd order section of the LTC1068 series has three outputs: the lowpass (LP) output, the bandpass (BP) output, and the highpass/notch (HP/N) output. These outputs are driven by internal operational amplifiers that can typically source 17 mA and sink 6 mA.

The output impedance of these pins is relatively low, allowing them to drive moderate loads. However, driving coaxial cables or resistive loads less than 20 kΩ will degrade the total harmonic distortion performance of any filter design. This degradation occurs because the output impedance of the filter interacts with the load impedance, creating a frequency-dependent voltage divider that distorts the filter's frequency response.

When evaluating the distortion or noise performance of a particular filter design implemented with an LTC1068 series device, the final output of the filter should be buffered with a wideband, noninverting high slew rate amplifier. This buffer isolates the filter output from the load, preventing load impedance from affecting the filter's performance. The buffer amplifier should have a slew rate of at least 10 V/μs to avoid slew-rate limiting of the filter output signal.

The output DC offset of each 2nd order section is specified as less than 5 mV typical. This low offset ensures that the filter output remains centered around the expected DC level, which is important for AC-coupled applications where the DC offset could be amplified by subsequent stages.

Wideband Noise, Clock Feedthrough, and Aliasing Phenomena in the LTC1068 Series

The wideband noise of the LTC1068 series filter is the total RMS value of the device's noise spectral density and is used to determine the operating signal-to-noise ratio. Most of the noise frequency content lies within the filter passband and cannot be reduced with post-filtering. For a notch filter, the noise of the filter is centered at the notch frequency.

The total wideband noise (in μV RMS) is nearly independent of the value of the clock frequency. This means that the noise performance remains consistent across the operating frequency range of the device. The clock feedthrough specifications are not part of the wideband noise measurement.

For a specific filter design, the total noise depends on the Q of each section and the cascade sequence. Higher Q values result in higher noise levels due to the increased gain in the passband. When multiple sections are cascaded, the noise from earlier stages is amplified by later stages, so the cascade sequence affects the overall noise performance.

Clock feedthrough is defined as the RMS value of the clock frequency and its harmonics that are present at the filter's output pins. The clock feedthrough is tested with the filter's input grounded and depends on printed circuit board layout and on the value of the power supplies. With proper layout techniques, the typical values of clock feedthrough are in the range of 50-100 μV RMS, depending on the specific variant and operating conditions.

Any parasitic switching transients during the rising and falling edges of the incoming clock are not part of the clock feedthrough specifications. Switching transients have frequency contents much higher than the applied clock, and their amplitude strongly depends on scope probing techniques as well as grounding and power supply bypassing. The clock feedthrough can be greatly reduced by adding a simple RC lowpass network at the final filter output. This RC network will completely eliminate any switching transients.

Aliasing is an inherent phenomenon of switched-capacitor filters and occurs when the frequency of the input signals that produce the strongest aliased components have a frequency such that the aliased component falls into the filter's passband. For an LTC1068 series device, the sampling frequency is twice the clock frequency (fCLK). If the input signal spectrum is not band-limited, aliasing may occur.

To prevent aliasing, the input signal should be band-limited to frequencies below half the sampling frequency (fCLK). This can be achieved by placing an antialiasing filter before the LTC1068 series device. The antialiasing filter should have a cutoff frequency below fCLK/2 and should provide sufficient attenuation at frequencies above fCLK/2 to prevent aliased components from entering the passband of the LTC1068 series filter.

Practical Design Implementation with the LTC1068 Series: Layout Considerations and Demonstration Platforms

Successful implementation of the LTC1068 series requires careful attention to printed circuit board layout and component placement. The compact nature of the 28-pin SSOP package allows for very compact filter implementations, with total board areas as small as 1 inch by 0.8 inches for an 8th order filter using 0603 size surface mount resistors and capacitors.

The analog ground plane is the foundation of a good layout. This plane should surround the LTC1068 series package and should be connected to any digital ground at a single point only. This single-point connection prevents ground loops that could introduce noise into the filter. All bypass capacitors should be connected to this analog ground plane with short traces to minimize inductance.

Power supply traces should be routed away from signal traces to prevent capacitive coupling. The clock signal should be routed from the right side of the IC package and perpendicular to it. Signal traces should be kept away from the inverting input pins of the internal operational amplifiers, with a minimum separation of 0.1 inches.

The LTC1068 series is supported by FilterCAD, a free filter design software for Windows that simplifies the design process. FilterCAD allows designers to enter filter specifications and automatically generates a complete schematic with component values. The software handles the complexity of selecting the appropriate operating mode and calculating the required external resistor values.

Demonstration Circuit 104 (DC104) is a surface mount printed circuit board available for evaluation of the LTC1068 series. The DC104 board is available in four assembled versions: Assembly 104-A features the LTC1068CG, Assembly 104-B features the LTC1068-200CG, Assembly 104-C features the LTC1068-25CG, and Assembly 104-D features the LTC1068-50CG.

All DC104 boards are assembled with input, output, and power supply test terminals, a 28-lead SSOP filter device, a dual operational amplifier in an SO-8 package for input or output buffers, and decoupling capacitors for the filter and operational amplifiers. Jumpers on the board configure the filter's second-order circuit modes, dual or single supply operation, and the operational amplifier buffers as inverting or noninverting. Surface mount pads are available on the board for 1206 size surface mount resistors, allowing designers to add external components for frequency tuning or other modifications.

Conclusion

The LTC1068 series represents a comprehensive solution for implementing switched-capacitor filters in applications ranging from ultralow frequency instrumentation to high-frequency signal processing. The family's four variants, each with different clock-to-center frequency ratios, provide designers with options that match their specific frequency range requirements. The low noise performance, flexible power supply options, and support for multiple operating modes make the LTC1068 series suitable for demanding applications where signal integrity and frequency accuracy are important. The availability of design software and demonstration boards further simplifies the implementation process, allowing designers to focus on their application requirements rather than the details of filter design.

Frequently Asked Questions (FAQ)

Q1. What is the difference between the four variants of the LTC1068 series, and how do I choose the right one for my application?

A1. The four variants differ in their internal clock-to-center frequency ratio: the LTC1068-200 has a 200:1 ratio for ultralow frequency applications, the standard LTC1068 has a 100:1 ratio for general-purpose filtering, the LTC1068-50 has a 50:1 ratio and is optimized for low-power single-supply operation, and the LTC1068-25 has a 25:1 ratio for high-frequency applications. Choose based on your target frequency range: use LTC1068-200 for frequencies below 25 kHz, LTC1068 for 1 Hz to 50 kHz, LTC1068-50 for low-power applications up to 50 kHz, and LTC1068-25 for frequencies up to 200 kHz.

Q2. Can the LTC1068 series operate from a single power supply, and what are the implications for circuit design?

A2. Yes, the LTC1068 series can operate from a single 5V or 3.3V supply in addition to dual ±5V supplies. In single supply mode, an internal resistive divider biases the analog ground pin to approximately half the supply voltage, creating a virtual ground point. This requires a 0.47 μF bypass capacitor on the AGND pin and affects the signal swing available around the virtual ground point, so circuit design must account for this reduced dynamic range compared to dual supply operation.

Q3. What is the significance of the center frequency accuracy specification of ±0.3% typical and ±0.8% maximum?

A3. This specification indicates how closely the actual center frequency of the filter matches the intended design frequency. The ±0.3% typical accuracy means that under normal conditions, the center frequency will be within 0.3% of the design value, while the ±0.8% maximum ensures that even in worst-case conditions (temperature extremes, supply voltage variations, component tolerances), the frequency will not deviate by more than 0.8%. This accuracy is maintained because the center frequency is determined by the clock frequency and internal ratios, not by external component tolerances.

Q4. How does the noise performance of the LTC1068 series compare across the different variants, and what factors affect noise in filter designs?

A4. The LTC1068-200 and standard LTC1068 produce 50 μV RMS of noise per 2nd order section, the LTC1068-50 produces 75 μV RMS, and the LTC1068-25 produces 90 μV RMS. Noise performance is affected by the Q value of each filter section—higher Q values result in higher noise due to increased passband gain. When cascading multiple sections, the cascade sequence matters: placing lower-Q sections before higher-Q sections minimizes noise accumulation. The total noise also depends on the specific filter topology and the number of cascaded sections.

Q5. What are the clock signal requirements, and what happens if the clock signal does not meet these specifications?

A5. The clock signal must be a TTL or CMOS square wave with a 50% duty cycle (±10%), with rise and fall times not exceeding 1 μs. The clock source should have a separate power supply isolated from the filter's power supply. If the clock signal does not meet these specifications, internal clock jitter will increase, degrading the filter's frequency accuracy and introducing noise. Sine waves are not recommended for clock frequencies below 100 kHz because their slow rise and fall times generate excessive jitter.

Q6. How do I prevent clock feedthrough and switching transients from degrading filter performance?

A6. Clock feedthrough can be minimized through proper printed circuit board layout: route the clock signal from the right side of the IC package perpendicular to it, place a 200 Ω resistor between the clock source and the clock input pin to slow rise and fall times, and maintain at least 0.1 inches separation between the clock trace and any inverting input pins. Switching transients can be eliminated by adding a simple RC lowpass network at the final filter output. Proper power supply bypassing and a high-quality analog ground plane also reduce clock feedthrough.

Q7. What is aliasing in the context of switched-capacitor filters, and how do I prevent it?

A7. Aliasing occurs when input signal frequencies above half the sampling frequency (fCLK/2) are reflected back into the filter's passband, creating false frequency components. For the LTC1068 series, the sampling frequency is twice the clock frequency. To prevent aliasing, the input signal must be band-limited to frequencies below fCLK/2 using an antialiasing filter placed before the LTC1068 series device. The antialiasing filter should provide sufficient attenuation at frequencies above fCLK/2 to prevent aliased components from entering the LTC1068 series filter's passband.

Q8. How do I select the appropriate operating mode (Mode 1, Mode 1b, Mode 2, or Mode 3) for my filter design?

A8. Mode 1 is the simplest, requiring no external resistors for frequency tuning, and is suitable for high-order Butterworth filters and cascaded bandpass functions. Mode 1b adds external resistors to adjust the frequency ratio beyond the nominal value while maintaining Mode 1's speed advantages, making it optimal for high-Q designs. Mode 3 is the classical state variable configuration offering maximum flexibility in frequency tuning but operating slower than Mode 1. Mode 2 combines advantages of Mode 1 and Mode 3 with reduced resistor tolerance sensitivity. Use FilterCAD software to automatically select the optimal mode for your specifications.

Q9. What load impedance should I use when driving the LTC1068 series outputs, and why is buffering sometimes necessary?

A9. The LTC1068 series outputs can source 17 mA and sink 6 mA. Loads below 20 kΩ will degrade total harmonic distortion performance because the output impedance interacts with the load impedance, distorting the frequency response. For applications where distortion or noise performance is critical, buffer the final filter output with a wideband, noninverting high slew rate amplifier (at least 10 V/μs). This buffer isolates the filter from the load, preventing load impedance from affecting filter performance.

Q10. How do I optimize the printed circuit board layout for the LTC1068 series to minimize noise and ensure stable operation?

A10. Create an analog ground plane surrounding the LTC1068 series package and connect it to digital ground at a single point only. Place 0.1 μF bypass capacitors on V+ and V- pins as close as possible to the device. Route power supply traces away from signal traces. Keep signal traces at least 0.1 inches away from inverting input pins. Route the clock signal from the right side of the package perpendicular to it. Use 0603 or smaller surface mount components to minimize parasitic inductance. For single supply operation, add a 0.47 μF bypass capacitor on the AGND pin. These practices minimize noise coupling and ensure stable filter operation.

Q11. What is the maximum Q value I can achieve with the LTC1068 series at a given frequency, and how does this affect filter design?

A11. The maximum achievable Q depends on the center frequency, power supply voltage, and operating temperature. The device documentation provides Maximum Q vs Center Frequency graphs that define the stability limits. A bandpass gain error of 3 dB or less is defined as stable operation. When passband gain error exceeds 1 dB, use a compensation capacitor (CC) connected from the lowpass node to the inverting node, with a value of approximately 5 pF per 1 dB of gain error (not exceeding 15 pF). When operating near the maximum Q limits, expect passband gain variations of 2 dB or more, which is normal for high-Q designs.

Q12. Can I use the LTC1068 series to implement filters with complex transfer functions like lowpass notch or allpass filters?

A12. Yes, complex transfer functions are achieved by summing two or more of the LP (lowpass), BP (bandpass), or HP/N (highpass/notch) outputs from different 2nd order sections or different modes. For example, a lowpass notch filter can be created by summing the lowpass output from one section with the notch output from another section. The FilterCAD software automatically handles these combinations and generates the required summing network. This flexibility allows the LTC1068 series to implement virtually any filter topology that can be decomposed into 2nd order sections.