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Ampere releases 80-core ARM processor: rushes to 128 core by the end of the yea
The ARM architecture is now very popular. Not only is it absolutely dominant in the mobile field, but it is also advancing in the data center, cloud services, and high-performance computing fields. Many manufacturers have released multi-core, high-frequency ARM processors. The upstart is also an ARM architecture, and even Apple is using the ARM architecture to develop its own chips.
Today, Ampere Computing (Ampere Computing) released its first generation of Altra series processors, mainly for large cloud service providers, known as the industry's first 80-core native cloud processor family, will rush to 128 cores by the end of the year.
Today, Ampere Computing (Ampere Computing) released its first generation of Altra series processors, mainly for large cloud service providers, known as the industry's first 80-core native cloud processor family, will rush to 128 cores by the end of the year.
The Ampere Altra processor is based on the ARM Neoverse N1 enterprise-level core architecture, four-shot super-scalar out-of-order execution, supports the ARM v8.2 instruction set, and draws on some features of ARM v8.3 and v8.5, with two SIMD 128 bits Unit, support FP16 floating point, INT integer arithmetic, TSMC 7nm process manufacturing.
All cores are connected in series through a Mesh grid network. Each core has 64KB first-level instruction cache, 64KB first-level data cache, and 1MB second-level cache. All cores share 32MB third-level cache, and all levels of cache support ECC.
The memory supports eight channels of DDR4-3200 ECC, up to two for each channel, a total of up to 16 single channels, and a maximum capacity of 4TB.
It supports single-channel or dual-channel parallel, each providing 128 PCIe 4.0 buses, of which 32 are used for interconnection and 96 external, dual-channel can provide 192 PCIe 4.0.
All cores are connected in series through a Mesh grid network. Each core has 64KB first-level instruction cache, 64KB first-level data cache, and 1MB second-level cache. All cores share 32MB third-level cache, and all levels of cache support ECC.
The memory supports eight channels of DDR4-3200 ECC, up to two for each channel, a total of up to 16 single channels, and a maximum capacity of 4TB.
It supports single-channel or dual-channel parallel, each providing 128 PCIe 4.0 buses, of which 32 are used for interconnection and 96 external, dual-channel can provide 192 PCIe 4.0.
The Altra series provides up to 11 models, the model name can be called an industry model, code name plus core number plus frequency, simple and clear, for example, the flagship "Q80-33" is 80 core (80 thread), 3.3GHz, thermal design function Consumption 250W-Q corresponds to the code name "QuickSilver" (Marvel character fast silver).
The other three 80 cores are 3.0GHz/210W, 2.6GHz/175W, 2.3GHz/150W, there is also a 72 core, four 64 cores, a 48 core, a 32 core, and the thermal design power consumption is at least 45W— —The thermal design power consumption of 32 cores filled with 4TB memory will rise to 58W.
The other three 80 cores are 3.0GHz/210W, 2.6GHz/175W, 2.3GHz/150W, there is also a 72 core, four 64 cores, a 48 core, a 32 core, and the thermal design power consumption is at least 45W— —The thermal design power consumption of 32 cores filled with 4TB memory will rise to 58W.
Next, Ampere will launch an enhanced version of the Altra Max series, code-named "Mystique" (Marvel character magic woman), the new chip design is still a grid network, the maximum number of cores reaches 128, memory, PCIe and other specifications are not Change, the sample in the fourth quarter, mass production next year.
Looking ahead, Ampere is also designing a new second-generation "Siryn" (Marvel character Sonic girl), the manufacturing process is upgraded by 5nm, the number of cores has been determined (unpublished), it is expected to support DDR5, PCIe 5.0, and the test chip has been taped out It is expected to be sampled by the end of next year.
Looking ahead, Ampere is also designing a new second-generation "Siryn" (Marvel character Sonic girl), the manufacturing process is upgraded by 5nm, the number of cores has been determined (unpublished), it is expected to support DDR5, PCIe 5.0, and the test chip has been taped out It is expected to be sampled by the end of next year.