AN983B-BG-T-V8

Frequently Asked Questions (FAQ)

Q1. What Ethernet speeds and modes does the AN983B-BG-T-V8 support?

A1. The AN983B-BG-T-V8 supports IEEE 802.3u 100BASE‑TX and IEEE 802.3 10BASE‑T. It can operate in both full‑duplex and half‑duplex at 10 Mbps and 100 Mbps. Auto‑negotiation selects the best common mode with the link partner, following this priority: 100BASE‑TX full‑duplex, 100BASE‑TX half‑duplex, 10BASE‑T full‑duplex, 10BASE‑T half‑duplex. When auto‑negotiation is disabled, speed and duplex are forced via PHY register 0.

Q2. Does the AN983B-BG-T-V8 include an integrated PHY, or is an external PHY required?

A2. The AN983B-BG-T-V8 integrates a full 10BASE‑T/100BASE‑TX PHY, including PCS, PMA, PMD, Manchester encoding/decoding, 4B/5B encoding/decoding, scrambler/descrambler, adaptive equalizer, baseline wander compensation, and MLT‑3 line driver. An external PHY is not required for standard twisted‑pair Ethernet. However, the AN983B-BG-T-V8 can be configured as a MAC‑only controller, in which case it exposes a standard MII interface to connect to external PHYs such as HomePNA or HomePlug devices.

Q3. What PCI bus capabilities are provided by AN983B-BG-T-V8?

A3. The AN983B-BG-T-V8 provides a 32‑bit PCI 2.2-compliant bus master interface operating at 0–33 MHz. It supports memory‑read, memory‑read‑line, memory‑read‑multiple, memory‑write, and memory‑write‑and‑invalidate commands as bus master. A PCI latency timer (performance meter) is available to tune bus usage. Network operation is specified at PCI system clock frequencies between 20 MHz and 33 MHz.

Q4. How does AN983B-BG-T-V8 manage transmit and receive buffers in host memory?

A4. The AN983B-BG-T-V8 uses descriptors in host memory to point to transmit and receive buffers. It supports two descriptor structures:

- Ring structure: Each descriptor has two buffers and supports receive early interrupt.

- Chain structure: Each descriptor has one buffer and a pointer to the next descriptor.

Transmit and receive buffers reside in host memory; a buffer contains one full packet or a segment of a packet, but not more than one packet. The OWN bit in each descriptor indicates ownership: OWN=1 for controller, OWN=0 for host. Descriptor and buffer addresses must be longword aligned.

Q5. How large are the on-chip FIFOs in AN983B-BG-T-V8, and how do they affect performance?

A5. The AN983B-BG-T-V8 has two independent long FIFOs, each 2 kB in size: one for transmit and one for receive. It can pre‑fetch up to two transmit packets into the transmit FIFO, reducing the inter‑frame gap (IFG) to approximately 0.96 µs and allowing minimum back‑to‑back packet transmission. Retransmissions after collisions can occur directly from FIFO (within 64 bytes) without rereading from host memory, which improves efficiency on congested links. The FIFOs also support automatic retransmission after under‑run, up to three retries.

Q6. Does the AN983B-BG-T-V8 support hardware-based flow control?

A6. Yes. The AN983B-BG-T-V8 supports IEEE 802.3x flow control via PAUSE frames in full‑duplex mode. It implements a MAC Control sublayer that recognizes MAC Control frames with Opcode 0x0001 and interprets the PAUSE time field (0–65,535 slot times). On receiving a valid PAUSE frame, the AN983B-BG-T-V8 starts a timer and inhibits new frame transmissions until the timer expires or a PAUSE frame with time=0 is received. This hardware-based flow control helps coordinate traffic with switches and bridges.

Q7. What mechanisms does AN983B-BG-T-V8 provide for Wake-on-LAN?

A7. The AN983B-BG-T-V8 supports PC99 wake-on-LAN via Magic Packet and programmable wake‑up patterns. It includes:

- Magic Packet detection (standard WoL frame format).

- Six wake‑up pattern filters, configured via CSR14 (WPDR).

- Each pattern uses offsets from 0–255.

- Programming a full pattern requires 25 consecutive long‑word writes to CSR14.

- Wake‑up Control/Status registers to enable or mask wake‑up sources and report which pattern triggered the event.

These capabilities allow the device to wake the system from low-power states when specific frames arrive.

Q8. How are the MAC address and multicast filters configured in AN983B-BG-T-V8?

A8. The MAC (physical) address is stored in PAR0 and PAR1 registers, automatically recalled from EEPROM on PCI reset. Example mapping: for MAC address 00-00-E8-11-22-33, PAR0 = 11 E8 00 00, PAR1 = xx xx 33 22. PAR0/PAR1 are readable and writable only when the receiver is stopped (CSR5 bits 19–17 = 000).

Multicast and unicast filters use 64‑bit hash tables in MAR0/MAR1 and unicast registers. The AN983B-BG-T-V8 calculates CRC32 over the destination address, then uses bits CRC[5:0] to select one of 64 entries:

- CRC[5] selects MAR1 vs. MAR0.

- CRC[4:0] selects bit position inside the double word.

Setting the corresponding bit in MAR0/MAR1 or unicast hash registers enables acceptance of frames with matching hashed addresses.

Q9. What non-volatile memory devices can be used with AN983B-BG-T-V8?

A9. The AN983B-BG-T-V8 supports:

- Boot ROM:

- Writeable Flash ROM or EPROM up to 128 KB.

- Accessible via PCI as byte, word, or double word.

- Flash can be updated via I/O port writes to specific control registers.

- Serial EEPROM:

- 93C46 or 93C66 devices.

- The AN983B-BG-T-V8 automatically reads 64 bytes from EEPROM after PCI reset to load device ID, vendor ID, subsystem IDs, MAC address, Maximum Latency, and Minimum Grant.

These devices allow configuration and identification data to persist across resets and power cycles.

Q10. How does one perform PHY diagnostics or internal loop-back tests using AN983B-BG-T-V8?

A10. PHY loop‑back is controlled via PHY register 0:

- Set bit 14 (Loopback) to 1 to enable internal loop‑back.

- In loop‑back:

- No frames are transmitted onto the wire (though idle MLT‑3 is still transmitted).

- In 100BASE‑TX, data is looped from the NRZ→NRZI converter output back into the NRZI→NRZ receiver path.

- In 10BASE‑T, data is looped from the Manchester encoder output into the receive PLL input.

This allows verification of the MAC/PHY data path without external cabling. Additionally, MAC loop‑back modes are provided for diagnostic purposes.

Q11. What are the power supply and I/O voltage requirements for AN983B-BG-T-V8?

A11. The AN983B-BG-T-V8 operates from a 3.3 V power supply and supports 5 V/3.3 V I/O tolerance on its relevant pins. DC specifications define input and output voltage levels for PCI, Flash/EEPROM, and MII interfaces. Separate internal power domains for 100BASE‑TX and 10BASE‑T allow power-down of one mode while the other remains active.

Q12. What package options are available for AN983B-BG-T-V8 and how should they be laid out on a PCB?

A12. The AN983B-BG-T-V8 is based on the AN983B/X family, offered in 128‑pin QFP and 128‑pin LQFP packages (with the AN983BLX variant in 128‑pin LQFP). Package outlines and dimension tables specify body size, lead pitch, and height.

Layout guidance includes:

- Place the controller close to the Ethernet transformer and keep traces to RJ45 short.

- Keep the crystal close to X1/X2 pins and away from Tx/Rx differential pairs and other high-frequency components.

- Route Tx+/Tx− and Rx+/Rx− as tightly coupled differential pairs with matched lengths and minimal right-angle bends.

- Use proper decoupling, wide power traces or planes, and continuous ground planes.

- Avoid power/ground planes directly under the transformer, and ensure transformer isolation voltage >2 kV.

Q13. How does the AN983B-BG-T-V8 handle collisions and back-off on a shared medium?

A13. In half‑duplex mode, the AN983B-BG-T-V8 asserts collision (COL) when simultaneous transmit and receive signals are detected. After enforcing a collision (jamming), it applies truncated binary exponential back‑off:

- For the nth retransmission attempt, the delay is r × slot_time, where 0 ≤ r < 2^k and k = min(n, 10).

This algorithm randomly spaces retransmission attempts to reduce repeated collisions when multiple nodes contend for the medium.

Q14. What timing considerations are important for connecting PCI and MII interfaces to AN983B-BG-T-V8?

A14. For the PCI interface:

- Observe PCI clock specifications (period, duty cycle, jitter) and maintain controlled skew.

- Maintain required setup and hold times for address/data and control signals as defined in PCI timing tables.

For the MII interface:

- Ensure TxD, Tx_EN, RxD, and Rx_DV meet the setup/hold times relative to Tx_CLK and Rx_CLK (see MII timing diagrams).

- Adhere to VIH(min) and VIL(max) levels for reliable logic detection.

For MDIO:

- MDIO and MDC must satisfy the timing relationships shown in the MDIO timing diagrams for both STA‑sourced and PHY‑sourced directions. Proper adherence to these constraints ensures successful PHY register access.

Q15. Can AN983B-BG-T-V8 be used in systems that require endian flexibility?

A15. Yes. The AN983B-BG-T-V8 supports both big‑endian and little‑endian byte ordering, configurable via its control registers. This allows it to integrate into host systems with different native endianness without requiring software-based byte swapping of packet data or descriptors.

Q16. What diagnostic and status information is available from AN983B-BG-T-V8 for driver development?

A16. The AN983B-BG-T-V8 exposes a rich set of registers:

- Status register (CSR5) and Assistant Status (CSR16) reporting:

- Transmit/receive completion.

- Errors (e.g., under‑runs, over‑runs, descriptor errors).

- Early interrupt triggers and other events.

- Interrupt Enable (CSR7) and Assistant Interrupt Enable (CSR17) to configure which events generate interrupts.

- Lost Packet Counter for dropped frame statistics.

- Current Working Transmit and Receive Descriptor Pointers to debug descriptor handling.

- PCI Bus Performance Counter to analyze bus utilization.

- PHY status registers (1, 5, 6 etc.) for link status, negotiation completion, and partner capabilities.

These registers facilitate driver development, performance tuning, and runtime diagnostics in AN983B-BG-T-V8-based designs.