ADAU1966AWBSTZ

Product Overview of the ADAU1966A 16-Channel DAC

The ADAU1966A represents a comprehensive solution for multi-channel audio conversion in professional and consumer applications. This single-chip digital-to-analog converter integrates 16 independent DAC channels, each capable of delivering high-fidelity audio output with differential or single-ended configurations. The device operates from industry-standard supply voltages of 2.5 V for digital circuits and 3.3 V for analog and I/O circuits, making it compatible with modern system architectures.

The ADAU1966A is housed in an 80-lead LQFP package and has been qualified for automotive applications, ensuring reliability in demanding environments. The device supports sample rates from 32 kHz to 192 kHz, accommodating everything from standard audio applications to high-resolution audio systems. With a total quiescent power consumption of 299 mW, the ADAU1966A balances performance with power efficiency, a consideration that becomes significant in battery-powered or thermally constrained systems.

Core Architecture and Signal Processing in the ADAU1966A

The ADAU1966A employs Analog Devices' patented multibit sigma-delta architecture to achieve its high-performance characteristics. Each of the 16 DAC channels incorporates on-chip digital interpolation filters with 68 dB stop-band attenuation and linear phase response. These filters operate at variable oversampling ratios depending on the sample rate: 256× for 48 kHz operation, 128× for 96 kHz, and 64× for 192 kHz modes.

The differential output configuration of the ADAU1966A channels provides inherent advantages in noise and distortion performance. At 48 kHz operation with differential outputs, the device achieves 114 dB dynamic range (A-weighted) and −97 dB total harmonic distortion plus noise. For single-ended outputs, these specifications are 110 dB and −95 dB respectively. This performance differential reflects the noise rejection benefits of differential signaling, where common-mode interference is naturally cancelled.

Each channel features an independently programmable attenuator with 255 steps in 0.375 dB increments, providing flexible gain adjustment across a range of approximately 95.625 dB. This fine-grained control allows system designers to optimize signal levels for downstream processing stages without requiring external gain circuits.

The ADAU1966A offers a low propagation delay mode specifically designed for 192 kHz operation. When enabled through register configuration, this mode reduces latency by trading off some audio frequency response and accepting increased out-of-band energy. This option proves valuable in real-time audio processing applications where delay must be minimized.

Analog Output Performance Characteristics of the ADAU1966A

The differential analog outputs of the ADAU1966A are voltage outputs with a nominal common-mode DC level of 1.5 V, derived from the 3.3 V analog supply. With a 0 dB full-scale digital input signal, each output pin swings approximately ±1.42 V peak, resulting in a differential swing of 5.66 V peak-to-peak across the two pins of a channel pair.

The output filter design significantly influences the realization of the ADAU1966A's specified performance. The differential outputs require only a single-order passive RC filter to achieve the specified dynamic range. However, for applications demanding more signal level or more robust filtering, a second-order active Bessel filter using a single operational amplifier can be implemented. The choice of filter components is critical; operational amplifiers with inadequate slew rate or bandwidth can cause high-frequency noise to fold into the audio band, degrading performance.

The ADAU1966A provides a common-mode reference pin (CM) that outputs the internal common-mode voltage. This pin can be used to bias external operational amplifiers to the common-mode voltage of the analog signal path. Proper buffering of this reference with a high-quality operational amplifier is recommended to prevent noise injection into the signal path.

Clock Management and Timing Flexibility in the ADAU1966A

The ADAU1966A incorporates an on-chip phase-locked loop that can derive the internal master clock from multiple sources, reducing the need for external high-frequency clock signals and thereby minimizing electromagnetic emissions. The PLL can be configured to lock to an external master clock at frequencies of 256×, 384×, 512×, or 768× the sample rate (referenced to 48 kHz mode).

In an alternative configuration, the ADAU1966A PLL can lock directly to the left-right frame clock (DLRCLK) without requiring an external master clock. This mode, when combined with internal bit clock generation, eliminates the need for high-frequency clock signals on the PCB, significantly reducing EMI emissions. A loop filter connected to the LF pin enables this low-EMI operation mode.

The ADAU1966A provides an MCLKO output pin that can be programmed to deliver various clock signals. The default configuration provides a buffered copy of the input master clock. Alternative settings allow MCLKO to output low-jitter clock signals at scaled frequencies: either 4 to 6 MHz or 8 to 12 MHz, with the exact frequency automatically scaled based on the input master clock frequency. The MCLKO pin can also be disabled entirely if not required by the system.

The device supports both master and slave modes for the serial audio interface. In slave mode (the default), the ADAU1966A accepts external bit clock and frame clock signals. In master mode, the device generates these signals internally, simplifying the system architecture when the ADAU1966A serves as the timing reference.

Serial Interface Options and Data Format Support in the ADAU1966A

The ADAU1966A provides multiple serial interface options to accommodate diverse system architectures. The device supports both I²C and SPI control protocols for register access and configuration. The I²C interface operates as a 2-wire bus with open-drain SDA and SCL lines, allowing multiple ADAU1966A devices to coexist on the same bus through address selection. The SPI interface operates in 24-bit mode with separate read and write operations, supporting burst transfers for efficient initialization.

For audio data transport, the ADAU1966A supports multiple serial audio interface formats. The default I²S format provides 1 BCLK delay between the frame clock edge and data transmission. Left-justified and right-justified formats are also available, with right-justified mode supporting both 24-bit and 16-bit data widths. These format options ensure compatibility with audio processors and microcontrollers from various manufacturers.

The ADAU1966A supports time-division multiplexed (TDM) modes for applications requiring high channel density on limited PCB routing. Four TDM configurations are available: TDM16 (single data line for all 16 channels), TDM8 (dual data lines with 8 channels each), TDM4 (quad data lines with 4 channels each), and TDM2 (eight data lines with 2 channels each). The frame clock can operate in either single-cycle pulse mode or 50% duty cycle mode, and the bit clock rate can be configured for either 16 or 32 BCLK cycles per channel slot.

An advanced feature of the ADAU1966A is the ability to operate without an explicit bit clock signal in TDM mode when the PLL locks to DLRCLK. This configuration further reduces EMI by eliminating high-speed clock signals from the PCB. Additionally, the device can latch data on the falling edge of DBCLK rather than the rising edge, effectively doubling the available setup time for high-speed TDM applications.

Power Supply Design and Voltage Reference Management in the ADAU1966A

The ADAU1966A requires careful power supply design to achieve its specified performance. The device operates from separate 3.3 V analog supplies (four AVDD pins) and 3.3 V I/O supply (IOVDD), along with a 2.5 V digital supply (DVDD). The power sequencing is critical: AVDDx and IOVDD must be settled at regulated voltages before DVDD is applied. When using the internal regulator of the ADAU1966A, this sequencing occurs automatically.

The ADAU1966A includes an integrated 2.5 V regulator driver that requires only an external pass transistor and bypass capacitors to generate the 2.5 V digital supply from the 3.3 V analog supply. This integrated regulator reduces external component count and simplifies board design. If the internal regulator is not used, VSUPPLY and VDRIVE should be connected to ground.

Proper bypassing of all power supply pins is essential for achieving the specified performance. Each power pin should be bypassed with a 100 nF ceramic capacitor placed as close as possible to the pin. Additionally, each power rail should have a bulk aluminum electrolytic capacitor of at least 22 µF on the same PCB as the device. The analog supply requires particular attention to cleanliness, as noise on this rail directly impacts the analog output performance.

The ADAU1966A includes an internal band gap voltage reference that generates the common-mode voltage for the analog outputs. This reference can be disabled if external common-mode biasing is required, allowing the CM pin to be driven from an external source. This capability enables dynamic adjustment of the output common-mode voltage based on system requirements, such as matching the clipping level of a power amplifier to its supply voltage.

Temperature Monitoring and Thermal Management in the ADAU1966A

The ADAU1966A integrates an on-board temperature sensor that monitors the silicon die temperature with ±3°C accuracy over a range of −60°C to +140°C in 1°C steps. The temperature sensor can operate in either continuous mode or one-shot mode. In continuous mode, the conversion rate is programmable from 0.5 seconds to 4 seconds between samples. In one-shot mode, a conversion is initiated by writing specific values to the control register, allowing faster sampling rates when needed.

The temperature sensor output is available through the THRM_TEMP_STAT register. The temperature in degrees Celsius is calculated by subtracting 60 from the register value. This temperature information can be used for thermal management, allowing the system to reduce power consumption or throttle performance if the device approaches thermal limits.

The ADAU1966A has thermal resistance characteristics suitable for standard PCB layouts. The junction-to-ambient thermal resistance is approximately 50°C/W on a 4-layer board with a solid ground plane. This specification allows designers to estimate the temperature rise above ambient for a given power dissipation level.

Volume Control and Channel Muting Capabilities in the ADAU1966A

The ADAU1966A provides comprehensive volume control and muting capabilities for each of the 16 channels. A master volume control register affects all channels simultaneously, while individual channel volume registers allow per-channel gain adjustment. Each volume control step corresponds to 0.375 dB, providing 256 steps across a range of 0 dB to −95.625 dB.

The volume control implementation uses logarithmic scaling, which aligns with human hearing perception. This approach allows natural-sounding volume adjustments across the full range. The volume control can be adjusted in real-time without introducing audible artifacts or clicks.

Each of the 16 channels can be individually muted through software control. The mute function is implemented as a soft mute, meaning the transition to and from the muted state is ramped to avoid audible popping sounds. This clickless muting capability is particularly important in consumer applications where audio artifacts are immediately noticeable.

The ADAU1966A also supports an auto-zero input mute function that automatically mutes channels when the input signal is zero. This feature can reduce noise floor in applications where channels are not always active.

Power Consumption Optimization in the ADAU1966A

The ADAU1966A offers multiple levels of power consumption optimization to suit different application requirements. Each of the 16 channels can be independently configured for one of four power/performance settings: best performance, good performance, low power, or lowest power. These settings adjust the internal bias current to the analog output amplifiers, trading off signal-to-noise ratio and total harmonic distortion for reduced power consumption.

At the best performance setting, the ADAU1966A achieves its specified 114 dB dynamic range and −97 dB THD+N for differential outputs. Selecting the good performance setting reduces power consumption by approximately 20% while maintaining nearly equivalent performance. The low power setting reduces consumption by approximately 40% with a corresponding reduction in SNR and THD+N. The lowest power setting achieves approximately 60% power reduction at the cost of further performance degradation.

Individual channel power settings can be controlled through four DAC_POWER registers, allowing different channels to operate at different performance levels based on their specific requirements. Alternatively, a global low power mode can be enabled through the PLL_CLK_CTRL1 register, applying the same power setting to all 16 channels simultaneously.

The ADAU1966A supports software power-down of individual functional blocks. The PLL can be powered down when using direct master clock mode. The temperature sensor can be disabled if thermal monitoring is not required. Individual DAC channels can be powered down through the PDN_CTRL2 and PDN_CTRL3 registers, reducing power consumption when fewer than 16 channels are needed.

Electromagnetic Interference Mitigation in the ADAU1966A

The ADAU1966A has been designed from the ground up to minimize electromagnetic interference emissions. The device uses 2.5 V digital supplies, which reduces the amplitude of digital waveforms compared to 3.3 V or 5 V logic, directly reducing EMI emissions. The continuous-time sigma-delta architecture further minimizes EMI compared to traditional switched-capacitor designs.

The on-chip PLL enables operation without a separate high-frequency master clock, eliminating one of the primary sources of EMI in audio systems. By locking the PLL to the DLRCLK signal, the ADAU1966A can generate all necessary internal clocks from a low-frequency frame clock signal. This configuration dramatically reduces the number of high-frequency signals on the PCB.

The internal bit clock generation feature further reduces EMI by eliminating the need for an external bit clock signal. When enabled, the ADAU1966A generates its own bit clock internally, synchronized to the frame clock. This configuration is compatible with both MCLKI/XTALI and DLRCLK PLL reference modes.

The ADAU1966A output pad drive strength is programmable, allowing designers to reduce EMI by using lower drive strength when the output signals do not need to drive long traces or heavily loaded buses. The default 4 mA drive strength can be increased to 8 mA if required by the application.

Operational Modes and Configuration Options in the ADAU1966A

The ADAU1966A supports a standalone mode that allows operation without a microcontroller connection. In this mode, the device is configured at power-up through the state of dedicated pins. The SA_MODE pin determines whether the device operates in standalone mode or program mode. When SA_MODE is tied to IOVDD, the device enters standalone mode with default register settings.

In standalone mode with both SA_MODE and SS/ADDR0/SA pins tied high, the device enters a TDM mode selected by the state of SA1 and SA2 pins. This configuration allows the ADAU1966A to operate as a complete audio subsystem without any microcontroller involvement, simplifying designs where the device serves as a fixed-function audio converter.

The ADAU1966A power-up sequence requires careful attention to ensure proper operation. The PU/RST pin must be pulled low initially and then driven high after power supplies have stabilized. The device requires 300 milliseconds to stabilize after the PU/RST pin is asserted high. The master power-up control (PUP) bit in the PLL_CLK_CTRL0 register can be used to place the device in an idle state while maintaining all register settings.

A soft reset function is available through the SOFT_RST bit in the PLL_CLK_CTRL0 register. This function resets all control registers to their default values while maintaining the internal clocks in default mode. Unlike a hard reset, the soft reset does not cause audible popping sounds at the analog outputs, making it suitable for use during operation.

The ADAU1966A supports direct master clock mode as an alternative to PLL operation. In this mode, a master clock at 512×fs (referenced to 48 kHz) must be supplied to the MCLKI pin, and the CLK_SEL bit in the PLL_CLK_CTRL1 register must be set to 1. The PLL should be powered down in this configuration through the PDN_THRMSENS_CTRL_1 register. However, the PLLVDD pin must still be connected to 2.5 V for the device to function properly.

Conclusion

The ADAU1966A represents a mature, feature-rich solution for multi-channel audio conversion applications. Its 16 independent DAC channels deliver high-fidelity audio performance with flexible output configurations supporting both differential and single-ended topologies. The device's comprehensive clock management capabilities, including an integrated PLL and support for multiple clock sources, enable low-EMI system designs that minimize high-frequency signals on the PCB.

The ADAU1966A's dual serial interface support (I²C and SPI) combined with multiple audio data format options ensures compatibility with diverse system architectures. The integrated temperature sensor, programmable power management, and flexible volume control capabilities provide system designers with the tools needed to optimize performance, power consumption, and thermal characteristics for specific applications. The automotive qualification of the ADAU1966A extends its applicability to demanding environments where reliability and performance consistency are paramount.

Frequently Asked Questions (FAQ)

Q1. What is the maximum number of channels the ADAU1966A can support, and can channels be operated independently?

A1. The ADAU1966A provides 16 independent DAC channels, each with its own volume control register and power management settings. Channels can be individually muted, powered down, or configured for different performance/power trade-off levels through the DAC_POWER registers. This independence allows flexible system designs where different channels can serve different functions or operate at different performance levels based on application requirements.

Q2. What are the key differences between differential and single-ended output configurations in the ADAU1966A?

A2. The ADAU1966A supports both differential and single-ended output configurations. Differential outputs provide superior noise and distortion performance, achieving 114 dB dynamic range and −97 dB THD+N compared to 110 dB and −95 dB for single-ended outputs. Differential outputs also provide better rejection of common-mode interference. Single-ended outputs simplify external circuitry but sacrifice some performance. The choice depends on the application's noise and distortion requirements and the complexity acceptable in the output filter design.

Q3. How does the ADAU1966A minimize electromagnetic interference in audio systems?

A3. The ADAU1966A employs several EMI reduction techniques: the on-chip PLL can lock to the low-frequency DLRCLK signal, eliminating the need for a separate high-frequency master clock; internal bit clock generation removes another high-frequency signal from the PCB; the 2.5 V digital supply reduces the amplitude of digital waveforms; and the continuous-time sigma-delta architecture inherently produces lower EMI than switched-capacitor designs. These features combined allow designers to create audio systems with significantly lower EMI emissions than traditional approaches.

Q4. What sample rates does the ADAU1966A support, and how does the internal clock architecture adapt to different rates?

A4. The ADAU1966A supports sample rates from 32 kHz to 192 kHz. The internal clock architecture adapts through programmable oversampling ratios: 256× for 48 kHz, 128× for 96 kHz, and 64× for 192 kHz modes. When the sample rate is changed, the master clock frequency remains constant, but the effective oversampling ratio adjusts accordingly. For example, a 12.288 MHz master clock provides 256×fs at 48 kHz, 128×fs at 96 kHz, and 64×fs at 192 kHz. This architecture allows a single master clock frequency to support multiple sample rates.

Q5. How should the power supplies be sequenced during ADAU1966A startup?

A5. The correct power sequencing is critical for proper ADAU1966A operation. AVDDx and IOVDD must be applied first and allowed to settle at their regulated voltages. DVDD should be applied after AVDDx and IOVDD are stable. The PU/RST pin should be pulled low initially, then driven high after all power supplies have stabilized. The device requires 300 milliseconds to stabilize after PU/RST is asserted high. If using the internal regulator, this sequencing occurs automatically. Improper sequencing can result in device malfunction or damage.

Q6. What is the purpose of the ADAU1966A's integrated temperature sensor, and how is it used?

A6. The ADAU1966A's integrated temperature sensor monitors the silicon die temperature with ±3°C accuracy over a range of −60°C to +140°C. The sensor can operate in continuous mode (with programmable conversion rates from 0.5 to 4 seconds) or one-shot mode (for faster sampling). The temperature information can be used for thermal management, allowing systems to reduce power consumption or throttle performance if the device approaches thermal limits. The temperature is read from the THRM_TEMP_STAT register and converted to degrees Celsius by subtracting 60 from the register value.

Q7. How does the ADAU1966A's volume control work, and what range of adjustment is available?

A7. The ADAU1966A provides both master volume control affecting all channels and individual per-channel volume controls. Each volume step corresponds to 0.375 dB, providing 256 steps across a range from 0 dB to −95.625 dB. The volume control uses logarithmic scaling that aligns with human hearing perception, allowing natural-sounding adjustments. Volume changes can be made in real-time without introducing audible artifacts. The soft mute function transitions smoothly to and from the muted state, avoiding clicks or pops.

Q8. What are the advantages of using the ADAU1966A's internal PLL compared to direct master clock operation?

A8. The ADAU1966A's internal PLL offers several advantages: it can lock to the low-frequency DLRCLK signal, eliminating the need for a separate high-frequency master clock and reducing EMI; it provides low-jitter clock signals that improve audio performance; it automatically scales the internal clock frequency based on the sample rate, allowing a single master clock frequency to support multiple sample rates; and it reduces the number of high-frequency signals on the PCB. Direct master clock operation is available as an alternative when the PLL is not needed, but the PLL is generally preferred for its EMI reduction and flexibility benefits.

Q9. Can multiple ADAU1966A devices be used in a single system, and how are they addressed?

A9. Yes, multiple ADAU1966A devices can be used in a single system. The I²C interface supports up to four devices on the same bus through address selection using the ADDR1 and ADDR0 pins. Each device can be assigned a unique address, allowing independent control of each device's registers. The SPI interface does not support multiple devices on the same bus, but separate SPI buses can be used for each device. This flexibility allows systems to scale to 32, 48, or more audio channels by using multiple ADAU1966A devices.

Q10. What output filter design is recommended for the ADAU1966A's differential outputs?

A10. The ADAU1966A's differential outputs require only a single-order passive RC filter to achieve the specified dynamic range performance. For applications requiring more signal level or more robust filtering, a second-order active Bessel filter using a single operational amplifier can be implemented. The choice of filter components is critical; operational amplifiers with inadequate slew rate or bandwidth can cause high-frequency noise to fold into the audio band, degrading performance. The common-mode reference pin (CM) can be used to bias external operational amplifiers to the common-mode voltage of the signal path.

Q11. How does the ADAU1966A support time-division multiplexed (TDM) audio data, and what are the available TDM configurations?

A11. The ADAU1966A supports four TDM configurations: TDM16 (single data line for all 16 channels), TDM8 (dual data lines with 8 channels each), TDM4 (quad data lines with 4 channels each), and TDM2 (eight data lines with 2 channels each). The frame clock can operate in either single-cycle pulse mode or 50% duty cycle mode. The bit clock rate can be configured for either 16 or 32 BCLK cycles per channel slot. TDM mode reduces PCB routing complexity by allowing multiple channels to be transmitted on fewer data lines, though at the cost of higher bit clock frequencies.

Q12. What power consumption levels can be achieved with the ADAU1966A's power management features?

A12. The ADAU1966A's total quiescent power consumption is 299 mW at full performance. Individual channels can be configured for different power/performance trade-offs: good performance reduces power by approximately 20%, low power by approximately 40%, and lowest power by approximately 60%. Individual channels can be powered down entirely when not needed. The PLL, temperature sensor, and voltage regulator can also be powered down independently. These features allow designers to optimize power consumption for specific applications, from always-on systems to battery-powered devices.

Q13. How should the ADAU1966A's analog supply be bypassed to achieve the specified performance?

A13. Proper bypassing of the analog supply is critical for achieving the specified performance. Each AVDD pin should be bypassed with a 100 nF ceramic capacitor placed as close as possible to the pin. Additionally, each analog power rail should have a bulk aluminum electrolytic capacitor of at least 22 µF on the same PCB as the device. The analog supply requires particular attention to cleanliness, as noise on this rail directly impacts the analog output performance. The common-mode reference pin (CM) and temperature sensor reference pin (TS_REF) should also be bypassed with parallel combinations of 10 µF and 100 nF capacitors placed close to the chip.

Q14. What is the purpose of the ADAU1966A's low propagation delay mode, and when should it be used?

A14. The ADAU1966A's low propagation delay mode is available for 192 kHz operation and reduces latency by trading off some audio frequency response and accepting increased out-of-band energy. This mode is enabled by setting specific bits in the DAC_CTRL0 register. It is useful in real-time audio processing applications where delay must be minimized, such as live sound reinforcement or interactive audio systems. The trade-off in frequency response and out-of-band energy must be evaluated for each application to determine if the latency reduction justifies the performance compromise.

Q15. How does the ADAU1966A support standalone operation without a microcontroller?

A15. The ADAU1966A can operate in standalone mode by tying the SA_MODE pin to IOVDD. In this mode, the device is configured at power-up through the state of dedicated pins (SA1 and SA2) that select the TDM mode. When both SA_MODE and SS/ADDR0/SA pins are tied high, the device enters a TDM mode determined by SA1 and SA2. This configuration allows the ADAU1966A to operate as a complete audio subsystem without any microcontroller involvement, simplifying designs where the device serves as a fixed-function audio converter with no need for runtime configuration changes.