According to South Korean media reports, Lee Jae-yong, de facto leader of Samsung Electronics, discussed Samsung's strategic plan to make chips using the world's first 3 nanometer process.
The report stated that Lee Jae-yong visited Samsung Electronics ’semiconductor R & D center in Hwaseong, Gyeonggi-do that day. This is also Lee Jae-yong's first official trip in 2020, during which he listened to Samsung Electronics' 3 nanometer process technology report and discussed the next-generation semiconductor strategy with the semiconductor department head.
According to Samsung Electronics, Lee Jae-yong discussed Samsung's plans to use the latest 3 nanometer all-gate (GAA) process technology under development to manufacture cutting-edge chips. GAA is considered to be an upgraded version of the current FinFET technology, which can ensure chip manufacturers to further reduce the chip size.
In April last year, Samsung Electronics completed the research and development of a 5-nm FinFET process technology based on extreme ultraviolet technology (EUV). Today, the company is working on the next generation of nanoprocess technology (ie, 3nm GAA). According to Samsung Electronics, compared with the 5-nanometer manufacturing process, the logic area efficiency of the 3-nanometer GAA technology has been improved by more than 35%, the power consumption has been reduced by 50%, and the performance has been improved by about 30%.
Regarding Lee Jae-yong ’s visit to the semiconductor R & D center, a Samsung spokesman said: “Lee Jae-yong ’s visit to the semiconductor R & D center today underlines once again Samsung ’s commitment to grow into the“ non-memory chip ”market Manufacturer's determination. "Currently, Samsung is already the world's largest maker of memory chips.
Last year, Samsung announced an investment plan of up to 133 trillion won (about 111.85 billion U.S. dollars), with the goal of becoming the world's largest SoC manufacturer by 2030.