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IP is evolving, LPDDR 5 is on the rise
The advancement of memory technology is like a "command baton", guiding the application to rejuvenate. With Xiaomi 10's world premiere of LPDDR5 becoming a hot spot, LPDDR5 has successfully become a "hot search".
As Low Power Double Data Rate (low power consumption memory), Xiaomi's first LPDDR has become a major wave of LPDDR5 waves, and it must be caused by the joint efforts of internal and external forces. On the one hand, emerging applications such as AI, 5G, and cloud computing have increased data throughput exponentially, requiring higher memory bandwidth to "complete" and become the driving force driving LPDDR to the next stage; on the other hand, upstream and downstream With the help of manufacturers, whether it is IP manufacturers such as Synopsys, or memory manufacturers such as Samsung, Micron and Hefei Changxin, as well as downstream manufacturers such as Xiaomi and Samsung, they all work together to promote the industrial chain and let LPDDR5 enter Fast lane. It follows that how to choose the ideal memory technology to meet the needs of the target application has become a new challenge.
As Low Power Double Data Rate (low power consumption memory), Xiaomi's first LPDDR has become a major wave of LPDDR5 waves, and it must be caused by the joint efforts of internal and external forces. On the one hand, emerging applications such as AI, 5G, and cloud computing have increased data throughput exponentially, requiring higher memory bandwidth to "complete" and become the driving force driving LPDDR to the next stage; on the other hand, upstream and downstream With the help of manufacturers, whether it is IP manufacturers such as Synopsys, or memory manufacturers such as Samsung, Micron and Hefei Changxin, as well as downstream manufacturers such as Xiaomi and Samsung, they all work together to promote the industrial chain and let LPDDR5 enter Fast lane. It follows that how to choose the ideal memory technology to meet the needs of the target application has become a new challenge.
Application Blossom
Compared with the previous generation of LPDDR4x, LPDDR5 has achieved a leapfrog upgrade in speed, power consumption and performance.
In February 2019, JEDEC released the LPDDR5 standard, which increased its speed from 3200Mbps in LPDDR4 to 5500Mbps, and can transfer 44GB of data per second. Moreover, LPDDR5 adopts the multi-bank group mode. Compared with LPDDR4x, it only supports Single Bank Group, which adds more parallel data channels and improves the data transmission bandwidth. In addition, in terms of power consumption, there are three sets of voltages inside LPDDR5, combined with the newly added DVFSC and DVFSQ functions, to further reduce power consumption by 20%.
From the perspective of Synopsys' IP product manager, in addition to the above advantages, LPDDR5 can also operate at a lower I / O voltage (0.5V). In addition, the LPDDR5 standard also has many higher RAS, namely reliability, availability, Maintainability characteristics. Therefore, LPDDR5 will be very popular in high-performance applications.
To undertake this wave of technological “upgrades”, currently mainstream manufacturers such as Samsung, Micron, and SK Hynix are competing in the LPDDR5 field. Domestic Hefei Changxin is accelerating its progress. After mass production of 8Gb DDR4, it is expected to manufacture LPDDR4 / 4X in the second half of this year, and LPDDR5 is still under planning.
For smartphone manufacturers who have been pursuing "lighter, faster, and stronger", adopting LPDDR5 also means faster, more power-saving, and better user experience. The flagship phones released by Samsung, Xiaomi and others all use LPDDR5 memory as the selling point. After opening this wave of "warm-up" market, it is expected that by the end of 2020, most mainstream flagship phones will also follow suit, including LPDDR5 into the Match ".
Moreover, not only in the smartphone market, LPDDR5 is also emerging in tablet PC applications. As cars become more automated and AI-based, more and more LPDDR5 will be adopted in the future. Obviously, LPDDR5 has become a trend in 2020, and the pace of LPDDR5 in the first year has already approached.
LPDDR5's "famous reputation" indicates that LPDDR technology has entered a new voyage, and it will also interact with industry applications.
IP boost
The vigorous rise of the LPDDR5 market is directly "positively related" to the performance of LPDDR5, which raises the most essential "question". How can SoC designers choose the appropriate IP to "match" the necessary performance, capacity, power and area? Just as the same IC design requires an effective combination of various IPs to realize value, LPDDR5 also requires IP's "God Assist" for its excellent performance.
Be aware that in order to meet the key functions of the LPDDR5 standard, such as speed, clock, operating voltage, DRAM topology, etc., the requirements for IP are of course also rising. Some IP manufacturers should keep up with the times and continue to introduce new ones at the LPDDR5 IP level to undertake a new round of technology detonation.
Synopsys engineers said that at the IP level, in addition to performance in terms of high bandwidth, low power consumption, 6400Mbps data rate support, and multiple functions to support low power consumption, it is more important to provide LPDDR5 controllers. , PHY, a comprehensive solution to verify IP.
To this end, the new ideas that are galloping in the field of IP move ahead, and in 2018, a new Design Ware memory interface IP solution was launched, supporting LPDDR5 SDRAM and constantly being improved. Recently, a proven HBM2E PHY IP core running at 3.6 Gbps was launched to create a more complete memory interface IP solution.
Fully unlocked
Compared with similar IPs, Synopsys LPDDR5 IP has refreshed the strength of innovation.
"One is to conduct firmware training through the embedded calibration processor in the PHY, optimize the memory training at startup to achieve the highest data reliability margin at the system level. At the same time, the training algorithm can be quickly updated without changing the hardware. The second is to input The use of decision feedback equalizer in the receiver reduces the impact of inter-symbol interference on improving signal integrity. The third is reliability, accessibility, and maintainability functions, including inline or error correction code, parity check, and data loop Redundancy check can reduce system downtime. Fourth, Synopsys' signal / power integrity expertise can accelerate design completion time and improve design credibility. "Synopsys engineers specifically introduced the advantages of IP.
As summarized by Synopsys engineers, Synopsys provides a complete IP solution. The LPDDR5 IP solution can run at 6400 Mb / s. The power consumption and area are optimized. The advanced functions support the latest LPDDR5 specifications. In addition, silicon verification IP can be used in a series of nodes including FinFET, which helps to accelerate the SoC design of the most complex applications in high-performance computing, automotive and mobile fields.
Perhaps the most important thing for storage makers is the importance of verifiable IP. The relevant person in charge of SK Hynix pointed out that SK Hynix is investing heavily in the development of powerful DRAM in order to provide higher capacity and processing speed. Through continuous cooperation with Synopsys, we can provide customers with fully tested and high-performance HBM DRAM solutions that are interoperable with DesignWare HBM2E IP cores to meet the capacity, throughput and power requirements of compute-intensive chips in advanced processes .
Particularly worth mentioning is that through TSMC's CoWoS advanced packaging technology verification, Synopsys DesignWare HBM2E PHY IP core provides a micro-bump array that meets the JEDEC HBM2E SDRAM standard, achieving the shortest 2.5D packaging path and the highest signal integrity.
Synopsys' LPDDR5 IP is not a "single player". Through years of accumulated EDA tools and IP advantages, Synopsys can also provide customers with hardening options, signal integrity / power integrity analysis, verification models, prototype design and Simulation supports such high added value.
Through this series of "Home Run" combinations, Synopsys' comprehensive memory interface IP core solutions including LPDDR5 / 4/3/2 IP cores have been fully verified in hundreds of design solutions and Used in millions of chips.
As highlighted by John Koete, Senior Vice President of Marketing, Synopsys Solutions, Synopsys provides a series of proven DesignWare memory interface IP core solutions with leading power, performance, and area advantages to meet the most challenging Throughput requirements.
Whether it is IP, storage vendors or application parties, it seems to be well prepared to work together to create and write the new value of the LPDDR5 industry chain.
Compared with the previous generation of LPDDR4x, LPDDR5 has achieved a leapfrog upgrade in speed, power consumption and performance.
In February 2019, JEDEC released the LPDDR5 standard, which increased its speed from 3200Mbps in LPDDR4 to 5500Mbps, and can transfer 44GB of data per second. Moreover, LPDDR5 adopts the multi-bank group mode. Compared with LPDDR4x, it only supports Single Bank Group, which adds more parallel data channels and improves the data transmission bandwidth. In addition, in terms of power consumption, there are three sets of voltages inside LPDDR5, combined with the newly added DVFSC and DVFSQ functions, to further reduce power consumption by 20%.
From the perspective of Synopsys' IP product manager, in addition to the above advantages, LPDDR5 can also operate at a lower I / O voltage (0.5V). In addition, the LPDDR5 standard also has many higher RAS, namely reliability, availability, Maintainability characteristics. Therefore, LPDDR5 will be very popular in high-performance applications.
To undertake this wave of technological “upgrades”, currently mainstream manufacturers such as Samsung, Micron, and SK Hynix are competing in the LPDDR5 field. Domestic Hefei Changxin is accelerating its progress. After mass production of 8Gb DDR4, it is expected to manufacture LPDDR4 / 4X in the second half of this year, and LPDDR5 is still under planning.
For smartphone manufacturers who have been pursuing "lighter, faster, and stronger", adopting LPDDR5 also means faster, more power-saving, and better user experience. The flagship phones released by Samsung, Xiaomi and others all use LPDDR5 memory as the selling point. After opening this wave of "warm-up" market, it is expected that by the end of 2020, most mainstream flagship phones will also follow suit, including LPDDR5 into the Match ".
Moreover, not only in the smartphone market, LPDDR5 is also emerging in tablet PC applications. As cars become more automated and AI-based, more and more LPDDR5 will be adopted in the future. Obviously, LPDDR5 has become a trend in 2020, and the pace of LPDDR5 in the first year has already approached.
LPDDR5's "famous reputation" indicates that LPDDR technology has entered a new voyage, and it will also interact with industry applications.
IP boost
The vigorous rise of the LPDDR5 market is directly "positively related" to the performance of LPDDR5, which raises the most essential "question". How can SoC designers choose the appropriate IP to "match" the necessary performance, capacity, power and area? Just as the same IC design requires an effective combination of various IPs to realize value, LPDDR5 also requires IP's "God Assist" for its excellent performance.
Be aware that in order to meet the key functions of the LPDDR5 standard, such as speed, clock, operating voltage, DRAM topology, etc., the requirements for IP are of course also rising. Some IP manufacturers should keep up with the times and continue to introduce new ones at the LPDDR5 IP level to undertake a new round of technology detonation.
Synopsys engineers said that at the IP level, in addition to performance in terms of high bandwidth, low power consumption, 6400Mbps data rate support, and multiple functions to support low power consumption, it is more important to provide LPDDR5 controllers. , PHY, a comprehensive solution to verify IP.
To this end, the new ideas that are galloping in the field of IP move ahead, and in 2018, a new Design Ware memory interface IP solution was launched, supporting LPDDR5 SDRAM and constantly being improved. Recently, a proven HBM2E PHY IP core running at 3.6 Gbps was launched to create a more complete memory interface IP solution.
Fully unlocked
Compared with similar IPs, Synopsys LPDDR5 IP has refreshed the strength of innovation.
"One is to conduct firmware training through the embedded calibration processor in the PHY, optimize the memory training at startup to achieve the highest data reliability margin at the system level. At the same time, the training algorithm can be quickly updated without changing the hardware. The second is to input The use of decision feedback equalizer in the receiver reduces the impact of inter-symbol interference on improving signal integrity. The third is reliability, accessibility, and maintainability functions, including inline or error correction code, parity check, and data loop Redundancy check can reduce system downtime. Fourth, Synopsys' signal / power integrity expertise can accelerate design completion time and improve design credibility. "Synopsys engineers specifically introduced the advantages of IP.
As summarized by Synopsys engineers, Synopsys provides a complete IP solution. The LPDDR5 IP solution can run at 6400 Mb / s. The power consumption and area are optimized. The advanced functions support the latest LPDDR5 specifications. In addition, silicon verification IP can be used in a series of nodes including FinFET, which helps to accelerate the SoC design of the most complex applications in high-performance computing, automotive and mobile fields.
Perhaps the most important thing for storage makers is the importance of verifiable IP. The relevant person in charge of SK Hynix pointed out that SK Hynix is investing heavily in the development of powerful DRAM in order to provide higher capacity and processing speed. Through continuous cooperation with Synopsys, we can provide customers with fully tested and high-performance HBM DRAM solutions that are interoperable with DesignWare HBM2E IP cores to meet the capacity, throughput and power requirements of compute-intensive chips in advanced processes .
Particularly worth mentioning is that through TSMC's CoWoS advanced packaging technology verification, Synopsys DesignWare HBM2E PHY IP core provides a micro-bump array that meets the JEDEC HBM2E SDRAM standard, achieving the shortest 2.5D packaging path and the highest signal integrity.
Synopsys' LPDDR5 IP is not a "single player". Through years of accumulated EDA tools and IP advantages, Synopsys can also provide customers with hardening options, signal integrity / power integrity analysis, verification models, prototype design and Simulation supports such high added value.
Through this series of "Home Run" combinations, Synopsys' comprehensive memory interface IP core solutions including LPDDR5 / 4/3/2 IP cores have been fully verified in hundreds of design solutions and Used in millions of chips.
As highlighted by John Koete, Senior Vice President of Marketing, Synopsys Solutions, Synopsys provides a series of proven DesignWare memory interface IP core solutions with leading power, performance, and area advantages to meet the most challenging Throughput requirements.
Whether it is IP, storage vendors or application parties, it seems to be well prepared to work together to create and write the new value of the LPDDR5 industry chain.