Pull-Up and Pull-Down Resistors: Value Selection, Calculations, and Troubleshooting

Pull-up and pull-down resistors prevent digital inputs and open-drain lines from floating, but the common 10 kΩ rule is only a starting point. The selected resistance must keep the released node within a guaranteed logic range, limit current and power when the node is asserted, and meet any applicable RC rise-time requirement. Supply tolerance, leakage, capacitance, startup behavior, and parallel pulls can narrow the usable range. This article explains how to calculate those limits, apply them to configuration inputs and 400 kHz I²C lines, and verify the finished circuit with a multimeter and oscilloscope.

Catalog

Figure 1. Pull-up and pull-down circuits showing default and asserted states.

Default Logic States and Floating Inputs

Valid HIGH, Valid LOW, and Undefined Voltage

A digital input has voltage ranges that the manufacturer guarantees as LOW and HIGH. The maximum voltage guaranteed as LOW is written as V_IL(max), while V_IH(min) is the minimum voltage guaranteed as HIGH. A voltage between those limits is not a third logic state. It is an undefined region in which the receiving circuit does not guarantee the interpreted value.

An undriven node is floating because no low-impedance source fixes its voltage. Leakage, stored charge, capacitive coupling, contamination, and even a measuring instrument can move it. The voltage may appear stable during one test and change with temperature, wiring, or probe position.

Standard CMOS inputs should not remain near their switching region. A slow or intermediate input can increase supply current and may cause repeated transitions. The permitted input transition rate is product-specific. TI’s floating-CMOS application report explains the associated current and oscillation risks [1].

Figure 2. Logic thresholds, a floating input, and a stable pulled-up input.

Pull-Up and Pull-Down Circuits

A pull-up connects the node to a positive logic supply and holds it HIGH while undriven. A switch or open-drain device overrides it by connecting the node to ground, with the resistor limiting current.

A pull-down connects the node to ground and holds it LOW until a switch or driver applies a valid HIGH.

The resistor must be weak enough to let the switch or driver override the default without excessive current, but strong enough to keep the released node beyond the applicable input threshold. In a dynamic circuit, it must also charge or discharge the node capacitance within the allowed transition time.

Where Pull Resistors Belong

Switches, Jumpers, and Connectors

Switches, jumpers, and connectors leave a signal open in at least one position. A pull resistor establishes the voltage during that condition. Examples include configuration straps, buttons, interlock switches, and cable-detect inputs.

Long cables add capacitance and coupled noise, while connectors, protection devices, or another board can add leakage. A lower resistance provides stronger bias but draws more closed-switch current.

A pull resistor does not debounce a contact. Bounce can produce several valid transitions without either level floating. Software timing, a suitable RC input network, or a debounce circuit handles that separate problem.

Unused and Temporarily Undriven Inputs

An unused input needs a valid voltage unless the datasheet specifies internal bias or bus hold. A permanent input may connect directly to a rail when permitted. Use a resistor if another source may later drive the pin because it limits contention current.

Three-state buses, pins during reset, and outputs from unpowered devices may be temporarily high impedance. Their default state must exist throughout that interval, not only after software enables an internal pull.

Several permanently tied input loads may share a resistor if their leakage currents are added. Independent signals must not be joined to save resistors. Unused outputs are generally left open unless their documentation specifies otherwise.

Open-Drain and Open-Collector Outputs

An open-drain CMOS output contains a low-side transistor that can pull the line LOW. When that transistor turns off, the output enters a high-impedance state and an external pull-up establishes HIGH. An open-collector bipolar output behaves similarly. The LOW edge is actively driven, while the HIGH edge normally follows the pull-up resistor and node capacitance.

Open-drain outputs can share one line because no device actively drives HIGH. The node is wired-AND in positive logic, or often called wired-OR when the signals are active-low.

Open-drain outputs can translate to another pull-up voltage only when the output, receiver, and power-off state permit it. The SN74LVC1G06, for example, supports open-drain level translation only within its specified output-voltage, leakage, and partial-power-down limits [2].

Texas Instruments currently lists the SN74LS06 as active. This older LS-family open-collector inverter allows its output to be pulled up to 30 V and supports up to 40 mA of sink current. Under the stated datasheet conditions, V_OL(max) is 0.7 V at I_OL = 40 mA for the SN74LS06. The 30 V value is an allowable output voltage, not an actively sourced HIGH level [3].

Figure 3. Comparison of push-pull and open-drain outputs.

Limits and Misuses of Pull Resistors

A pull resistor cannot replace the specified termination of a differential bus, transmission line, or analog interface. Termination networks are selected from the line impedance, signaling method, and interface specification.

Push-pull outputs must not be tied together because opposing output states cause contention. A weak pull resistor may, however, establish a default state while a push-pull output is high impedance during reset, startup, or an unpowered interval.

Once the push-pull output becomes active, the resistor acts as a static load whenever the output drives against the pull direction. That current must be included when checking V_OH(min), V_OL(max), output current, resistor power, and supply consumption.

The pull voltage must remain inside every connected pin’s operating and power-off limits. A pull-up connected to an active rail can inject current through an unpowered device’s protection structure unless the pin has suitable overvoltage tolerance or an I_off specification.

Choosing the Default Direction

Active Polarity and Fail-Safe Behavior

The signal’s safe state determines whether it should default HIGH or LOW. An active-low reset input commonly uses a pull-up so the circuit remains out of reset when no device asserts the line. An active-high enable often uses a pull-down so the controlled load remains off until commanded. An active-low chip-select line usually defaults HIGH to prevent an unintended transaction.

These are not universal choices. A motor controller, power converter, or safety interlock may require a different state during a broken wire, controller reset, or loss of power. The design should identify the safe output condition first, then translate that condition into the required logic level and resistor direction.

Reset, Startup, and Unpowered States

Firmware-configured pulls may not control a pin during power-on reset, boot-ROM execution, deep sleep, or an unpowered state. Boot straps and hardware enables therefore often use external resistors. The processor’s reset-state pin table should be checked for default mode, internal pull direction, alternate functions, and the time at which software takes control.

Power sequencing adds another constraint. If V_PU rises before the receiving device’s V_CC, the input can be above its powered-off rating. A product with I_off circuitry may tolerate that condition within its specified voltage and leakage limits.

Without that feature, the design may require a switched pull-up, a different rail, a series current limit, or a device selected for partial-power-down operation.

Calculating the Resistor Value

Datasheet Parameters and Worst-Case Conditions

Collect the driver, receiver, pull rail, interconnect, and resistor limits before calculating resistance.

Area	Parameters to Check	Use in the Calculation
Receiving Input	VIH(min), VIL(max), input current or leakage, input capacitance, transition-rate limit	Establishes valid logic levels and DC or timing limits
Open-Drain Driver	VOL(max) at its stated IOL, off-state leakage, allowable output-voltage range, Ioff	Establishes LOW-state current, released-state leakage, and voltage compatibility
Pull Rail	Minimum and maximum voltage, startup sequence	Sets worst-case HIGH margin and asserted current
Interconnect	Trace, cable, connector, pin, and probe capacitance, external leakage	Sets total leakage and RC transition time
Resistor	Nominal value, tolerance, temperature coefficient, power rating, maximum continuous working voltage, overload or pulse-voltage rating	Determines worst-case resistance, current, dissipation, and voltage stress

Use guaranteed limits for pass-or-fail calculations. Typical curves can estimate behavior but do not replace those limits. For a pull-up, include leakage that pulls the node down. For a pull-down, include leakage that pushes it up.

Power rating alone does not establish whether a resistor can withstand the applied voltage. This matters in higher-voltage open-collector circuits, where a resistor may remain below its power limit but exceed its maximum continuous working voltage.

Check the resistor series datasheet for its maximum continuous working voltage and any applicable overload or pulse-voltage rating. Pulse capability can depend on pulse duration, repetition rate, resistance value, package size, and temperature. PCB creepage and clearance must be checked separately for the applied voltage and environment.

Input Pull-Up and Pull-Down Limits

For a released input with a pull-up, the maximum DC resistance is:

R_PU(max,DC) = (V_PU(min) - V_IH(min))/(I_leak(total))

where:

• R_PU(max,DC) is the largest pull-up resistance in ohms

• V_PU(min) is the lowest pull-up supply in volts

• V_IH(min) is the receiver’s minimum guaranteed HIGH voltage in volts

• I_leak(total) is the worst-case current in amperes that pulls the node downward

For a pull-down, the corresponding maximum resistance is:

R_PD(max,DC) = (V_IL(max))/(I_leak(total))

where I_leak(total) is the worst-case current that pushes the node upward.

The lower resistance limit comes from override current and output voltage. A device overriding a pull-up must keep V_OL below V_IL(max) at the resulting sink current. A source overriding a pull-down must keep V_OH above V_IH(min).

LS-family TTL shows why the two pull directions are not symmetrical. TI publishes the following threshold and input-current limits under the listed test conditions [4] [5].

Input Example	Supply and Temperature Conditions	Guaranteed Input Thresholds	Datasheet Input-Current Test Conditions
SN74LS00	VCC = 4.75 V to 5.25 V; TA = 0 °C to 70 °C	VIH(min) = 2.0 V; VIL(max) = 0.8 V	IIH(max) = 20 µA at VCC = 5.25 V and VI = 2.7 V; IIL(max) = −0.4 mA at VCC = 5.25 V and VI = 0.4 V
SN74LVC1G00	Thresholds at VCC = 3.0 V to 3.6 V; TA = −40 °C to 125 °C	VIH(min) = 2.0 V; VIL(max) = 0.8 V	II = ±5 µA at VI = 5.5 V and VCC = 0 V to 5.5 V; II = ±5 µA at VI = GND and VCC = 0 V to 5.5 V

For one SN74LS00 input, using the published maximum input-current magnitudes as engineering design currents gives:

R_PU(max,calc) = (4.75 V - 2.0 V)/(20 µA) = 137.5 kΩ

The corresponding pull-down calculation is:

R_PD(max,calc) = (0.8 V)/(0.4 mA) = 2.0 kΩ

These are engineering calculations based on published current limits, not manufacturer-specified pull-resistor limits. The I_IH and I_IL values are specified at their stated input-voltage test points, so the results should be treated as first-pass calculated bounds.

Both results also sit at the logic threshold with no added noise or tolerance margin. Sum the worst-case currents for multiple inputs and select a value that retains adequate margin across supply, resistance, and temperature tolerances.

Open-Drain Resistor Limits

An open-drain pull-up must satisfy its asserted LOW and released HIGH states. A common LOW-state bound is:

R_PU(min) = (V_PU(max) - V_OL(max))/(I_OL(allowed))

I_OL(allowed) is the sink current at which the driver guarantees V_OL(max). For a hard current ceiling, also check:

R_{PU(min,current)} = (V_PU(max))/(I_sink(limit))

The released-state DC maximum is:

R_PU(max,DC) = (V_PU(min) - V_IH(min))/(I_off(max) + Σ I_{input - leak(max)})

Include driver off-state leakage and every receiver, connector, protection, and measurement leakage path that pulls the node down.

Capacitance can impose a lower maximum resistance. For an exponential rise measured from 30% to 70%:

t_r = 0.8473R_PC_node

Therefore:

R_PU(max,rise) = (t_r(max))/(0.8473C_node)

The 0.8473 factor applies only to the 30%-to-70% thresholds. The final resistor must satisfy:

max[ R_PU(min) ] ≤ R_PU ≤ min[ R_PU(max,DC),R_PU(max,rise) ]

If the window has no overlap, reduce capacitance or speed, increase driver capability, or use an active or segmented bus.

Rise Time, Noise, and Power Tradeoffs

A lower resistance strengthens bias and accelerates a passive edge, but raises current and power while the line is LOW:

I_LOW ≈ (V_PU - V_OL)/(R_PU)

P_R ≈ ((V_PU - V_OL)²)/(R_PU)

A higher resistance reduces static loss but increases sensitivity to leakage, noise, and capacitance. Very fast edges can also increase ringing on long interconnects.

Multiple pull-ups on the same line act in parallel. Their equivalent resistance is:

(1)/(R_EQ) = (1)/(R₁) + (1)/(R₂) + … + (1)/(R_n)

Count pull-ups already fitted to development boards or modules before checking current and rise time.

Worked Design Examples

The following examples are calculated design checks based on cited limits. They are not laboratory measurements.

3.3 V Configuration Input

This worked example uses an SN74LVC1G00 input with a 10 kΩ pull-up to a 3.3 V ±0.3 V rail. The pull-up rail is assumed to track the device’s V_CC. A jumper set only while power is off asserts LOW [5].

Known values and assumptions are:

V_PU(min)​=3.0 V

V_PU(max)​=3.6 V

• V_IH(min)=2.0 V for V_CC=3.0 V to 3.6 V

• Input leakage opposing the pull-up = 5 µA maximum

• Candidate RPU=10 kΩ±5%

• Board leakage and jumper resistance are initially neglected

The maximum pull-up resistance from the input threshold is:

R_PU(max) = (3.0 V - 2.0 V)/(5 µA) = 200 kΩ

The candidate’s highest resistance is 10.5 kΩ. Its minimum released-input voltage is:

V_IN(min) = 3.0 V - (5 µA)(10.5 kΩ) = 2.9475 V

This result remains 0.9475 V above V_IH(min). With the jumper installed, the resistor’s minimum value of 9.5 kΩ produces the largest current:

I_{asserted(max)} = (3.6 V)/(9.5 kΩ) = 0.379 mA

P_R(max) = ((3.6 V)²)/(9.5 kΩ) = 1.36 mW

The value passes this DC check with wide voltage margin and low dissipation. Add any board leakage to 5 µA. A changing input would also require a transition-rate and capacitance check.

400 kHz I²C Bus

This example sizes one pull-up for each SDA and SCL line of a Fast-mode I²C bus using NXP UM10204 [6].

Known values and assumptions are:

• Bus mode = Fast-mode, up to 400 kbit/s

• V_PU = 3.3 V ± 5%, so V_PU(max) = 3.465 V

• V_OL(max) = 0.4 V at I_OL = 3 mA

• Estimated bus capacitance C_b = 200 pF

• Maximum 30%-to-70% rise time t_r(max) = 300 ns

• Candidate resistor = 1.50 kΩ ± 1%

• Every connected device supports the stated mode and voltage

The LOW-state minimum resistance is:

R_P(min) = (3.465 V - 0.4 V)/(3 mA) = 1.02 kΩ

The rise-time maximum is:

R_P(max) = (300 ns)/(0.8473(200 pF)) = 1.77 kΩ

The range established by the LOW-state and rise-time checks is approximately 1.02 kΩ to 1.77 kΩ. A 1.50 kΩ ±1% resistor spans 1.485 kΩ to 1.515 kΩ and remains inside that window.

A final bus design must separately verify the released-state DC limit using the worst-case leakage and V_IH(min) of every connected device. Those device-specific values are not assumed here.

Using the highest resistance for the slowest rise gives:

t_{r(max,calculated)} = 0.8473(1.515 kΩ)(200 pF) = 257 ns

At the lowest resistor value and V_OL = 0.4 V, the LOW-state current is:

I_LOW = (3.465 V - 0.4 V)/(1.485 kΩ) = 2.06 mA

The resistor’s worst idealized dissipation with the line at 0 V is:

P_R(max) = ((3.465 V)²)/(1.485 kΩ) = 8.08 mW

The 1.50 kΩ value passes the stated LOW-state and rise-time checks. The 200 pF estimate must include pins, routing, connectors, and the probe. Combine module pull-ups in parallel and measure both lines.

Above approximately 200 pF, NXP describes current-source or switched pull-up options for Fast-mode buses [6].

Figure 4. Calculated 400 kHz I²C pull-up example.

Internal and External Pull Resistors

Strength, Tolerance, and Reset Availability

Microcontroller pulls often use MOS devices or current sources rather than precision resistors. Their effective resistance varies with supply, process, and temperature, and their availability depends on reset and power mode.

STMicroelectronics AN4899 Rev. 4 gives approximately 40 kΩ as a typical internal GPIO pull-up/pull-down resistance in its general STM32 GPIO discussion. This is not a guaranteed value for every STM32 device. The exact MCU datasheet must be checked for device-specific resistance limits, reset state, and power-mode behavior [7].

Internal pulls suit local, slow inputs when their tolerance and reset state are acceptable. External resistors provide a predictable value before firmware runs and for cables, noisy environments, or timing-controlled buses.

Selection Table

Requirement	Internal Pull	External Pull	Combined Use
No added component	Best fit	Adds BOM and PCB area	Adds a component
Defined state during reset	Only if explicitly specified	Independent of firmware when its rail is valid	Verify both directions and reset modes
Tight resistance or RC timing	Often unsuitable	Available with specified tolerance	Calculate the parallel equivalent
Local button or static input	Often suitable	Useful for stronger bias	Check closed-state current
I²C or another timing-limited open-drain line	Do not assume adequacy	Normally selected from bus limits	Internal pull changes effective resistance
Long wire or higher leakage	May be too weak	Can provide a lower impedance	Account for total current

Opposing pulls form a divider. Same-direction pulls reduce equivalent resistance. Check both conditions in every firmware mode.

Testing and Troubleshooting

Static Voltage and Resistance Checks

On a powered low-voltage circuit, measure the released and asserted signal relative to logic ground. Compare the results with V_IH(min) and V_IL(max) with margin. The asserted voltage and known resistance can also reveal unexpected current.

Measure resistance only after de-energizing and discharging the circuit. Other resistors, protection paths, and internal pulls affect an in-circuit reading. Isolate the resistor or connected module when needed.

A multimeter can influence a weak node. A reading that stabilizes only with the meter attached indicates inadequate bias or another fault.

Oscilloscope Rise-Time Checks

A 10× probe normally adds less capacitance than a 1× probe, but it still contributes to C_node. Use a short ground connection to the same logic reference.

For I²C, measure rise time between 0.3 × V_DD and 0.7 × V_DD, as defined by UM10204 [6]. These thresholds match the 0.8473RC rise-time equation used earlier.

The waveform can expose a stuck-LOW device, ringing, repeated crossings, or a slow edge. Standard CMOS inputs may specify a transition limit in ns/V. Use a suitable Schmitt input when a slow or noisy edge cannot meet that limit.

Figure 5. DMM, oscilloscope, and resistance measurement methods.

Failure Symptoms and Corrective Actions

Symptom	Checks	Corrective Action
Random input transitions	Pin mode, missing or open resistor, long cable, noise, leakage	Restore a defined pull, reduce impedance if calculations allow, shorten or shield the connection, or use a suitable Schmitt input
Released node does not reach HIGH	Pull-up value, VPU, total leakage, another device pulling LOW	Correct the rail, lower resistance within sink-current limits, or isolate the loading device
Node does not reach LOW	Pull-down value, opposing internal pull, switch resistance, driver VOL	Reduce the pull-down within source-current limits, disable the conflicting pull, or repair the switch path
Correct DC level but bus errors remain	Rise time, bus capacitance, parallel pull-ups, probe loading	Recalculate the resistor window, reduce capacitance, change bus speed, or segment the bus
Excessive asserted current	Resistance too low, duplicated module pull-ups, wrong pull voltage	Increase the effective resistance while retaining timing and threshold margin
Wrong state during startup	Reset pin mode, internal pull availability, rail sequence	Add or change an external pull and verify the unpowered-pin rating
Several events from one button press	Contact bounce	Apply software or hardware debouncing rather than only changing the pull resistor
Line powers an unpowered device	Pin voltage and Ioff or clamp-current specifications	Use a compatible pin, change the pull rail, switch the pull-up, or limit injected current as the datasheet permits

Conclusion

A pull resistor is properly selected only after the complete operating window has been checked. The released state must satisfy the applicable input threshold, the asserted state must remain within the driver’s source or sink limits, and timing-limited nodes must meet their capacitance-dependent transition requirement. Internal pulls, resistor tolerance, leakage, duplicated module pull-ups, reset modes, and power sequencing can alter the result. Static voltage checks and oscilloscope rise-time measurements should confirm the calculations on the assembled circuit. If no resistor value satisfies every limit, the design must reduce capacitance, change speed or drive capability, revise the pull rail, or use a different bus arrangement.

Technical References:

[1] Texas Instruments, Implications of Slow or Floating CMOS Inputs, Application Report SCBA004, Rev. E.

[2] Texas Instruments, SN74LVC1G06 Single Inverter Buffer or Driver With Open-Drain Output, datasheet Rev. AB, October 2025.

[3] Texas Instruments, SNx4LS06 Hex Inverter Buffers and Drivers With Open-Collector High-Voltage Outputs, datasheet Rev. F, July 2016.

[4] Texas Instruments, SNx400, SNx4LS00, and SNx4S00 Quadruple 2-Input Positive-NAND Gates, datasheet Rev. D, May 2017.

[5] Texas Instruments, SN74LVC1G00 Single 2-Input Positive-NAND Gate, datasheet Rev. AC, August 2026.

[6] NXP Semiconductors, UM10204 I²C-Bus Specification and User Manual, Rev. 7.0, October 1, 2021.

[7] STMicroelectronics, Guidelines for GPIO Hardware Settings and Low-Power Consumption on STM32 MCUs, AN4899 Rev. 4, May 2026.

Frequently Asked Questions [FAQ]

1. Does a Pull Resistor Prevent Metastability in an Asynchronous Input?

No. It defines the idle voltage but cannot synchronize a signal with the receiving clock. Asynchronous inputs still require a synchronizer, handshake circuit, or asynchronous FIFO, depending on the signal type.

2. How Can a Pull Resistor Affect Sleep-Mode Battery Life?

Current flows whenever an external device holds the node opposite the pull direction. The approximate current is the voltage across the resistor divided by its resistance, so even a small continuous current can reduce battery runtime.

3. What Happens When a Pulled GPIO Is Switched to Analog-Input Mode?

The pull resistor can bias the analog source, form a voltage divider with its output impedance, and alter the ADC reading. Internal pulls should normally be disabled unless their effect is included in the analog design.

4. Where Should a Pull-Up or Pull-Down Resistor Be Placed on the PCB?

Place the resistor where it keeps the high-impedance portion of the trace short, usually close to the receiving input. For a connector or switch signal, place it on the receiver side so disconnecting the cable still leaves the input biased. On a short shared open-drain bus, electrical value and total capacitance usually matter more than exact placement, but stubs should remain short and duplicated module pull-ups must be counted.

5. How Is Average Pull-Up Resistor Power Estimated for a Changing Line?

If the line is LOW during a duty fraction D_LOW, the average resistor power is approximately:

P_R(avg) ≈ D_LOW((V_PU - V_OL)²)/(R_PU)

Use the continuous LOW case for the resistor rating if a fault can hold the line asserted.